Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization

Thakker, Rajesh A.; Baghini, Maryam Shojaei; Patil, Mukesh D.

doi:10.1109/vlsi.design.2009.14

Cited by 42 publications

(34 citation statements)

References 7 publications

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“…The error function is calculated based on simulation results produced by the circuit simulator. The error function (Ferror) is defined by the following equation [11],…”

Section: Methodsmentioning

confidence: 99%

“…These algorithms have also been used to a lesser degree for optimization of CMOS based analog circuits. Some notable works are [8] [9] [10] [11]. In [8] ABC, DE and PSO algorithms were used to optimize CMOS Miller OTA.…”

Section: Introductionmentioning

confidence: 99%

“…In [10], the performance of HS and DE algorithms were compared, the authors also derived the same conclusion. In [11], ultra-low power CMOS Miller OTA and a three-stage CMOS Miller op-amp were optimized by GA, PSO, and a modified PSO entitled HPSO and concluded that HPSO converges better than the others. In [1], HS, standard PSO (SPSO) 1995, and SPSO 2007 were compared.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Optimization of CMOS Miller OTA using Differential Evolutionary Algorithm

Prajapati

Acharya

Shah

2019

ijisae

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The circuit parameters of CMOS based analog and mixed-signal circuits conventionally are achieved by skilled engineers. Due to the progress of Moore's assumption and the growing complication of physical MOSFET models, the attention towards automation of CMOS based analog circuit design is increased. The issue of the automatic design of analog circuit has been tracked in the academy and industry since more than last two decades. In this paper, application of differential evolution (DE) algorithm is presented for the optimization of CMOS Miller Operational Transconductance Amplifier (OTA). DE algorithm has been developed using C language to optimize the CMOS Miller OTA. The error function of optimization for this circuit depends on desired specifications like voltage gain, phase margin (PM), unit gain bandwidth (UGB), power consumption, common mode rejection ratio (CMRR), slew rate (SR), power supply rejection ratio (PSRR), and a total MOS transistor area. Ngspice circuit simulator has been used as an error function creator and evaluator. BSIM3v3 MOSFET models with 0.18 µm and 0.35 µm CMOS technology have been used to simulate this circuit. The simulation results of this work are presented and compared with previous works reported in the literature.

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“…The error function is calculated based on simulation results produced by the circuit simulator. The error function (Ferror) is defined by the following equation [11],…”

Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Optimization of CMOS Miller OTA using Differential Evolutionary Algorithm

Prajapati

Acharya

Shah

2019

ijisae

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“…In this paper, well will focus on a three-level optimization cascade and novel visualization techniques, which are demonstrated for commonly used circuits [2][3][4][5] nominal sizing on schematic level.…”

Section: Introductionmentioning

confidence: 99%

Multi-objective optimization and visualization for analog design automation

Kammara

Palanichamy

König

2016

Complex Intell. Syst.

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The automated design of analog and mixed-signal circuits is a well-known subject of increasing technical and economical significance, e.g., sensory circuits for internet of things, cyber-physical systems, and Industry 4.0.The demand for rapid solution achievement under constraints, as, e.g., robustness, in established and emerging technologies as well as the migration between technologies gives incentive to automation activities. Existing approaches and tools still show improvement potential with regard to multivariate modeling, efficient and multi-objective optimization, as well as transparence and user interaction options during the design. This paper presents new approaches applied within an emerging design environment, denoted as ABSYNTH, with an evolving self-learning architecture for efficient hierarchical optimization in a cascade, which includes function approximators and simulators trained by proven evolutionary optimization algorithms, as well as a novel domain-specific visualization of the optimization space and the trajectory of the design process. Nominal schematic-level sizing of the commonly used Miller, buffer, and folded-cascode amplifier circuits has been studied with our approach. For Miller, buffer, and folded-cascode, a cascade of harmony search and particle swarm optimization on SVR, ngspice, and cadence simulators was found to be roughly 4 times, 2.5 times, and 2.5 times faster, respectively, than the flat approach with equal or better results. In future work, we will improve the approach B Abhaya Chandra Kammara

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“…Using this technique, the design with desired output response can be found. There are various optimization methods (deterministic and stochastic) used for this, such as Geometric Programming, Genetic Optimization, Particle Swarm Optimization etc [1] [2] [3]. Based on such design flow, circuits are designed for particular output but these methods do not provide the solution when an output is required at a target value with minimum variations due to noise.…”

Section: Introductionmentioning

confidence: 99%