Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology

Abstract

In this paper, we present a fully integrated CMOS LNA (low noise amplifier) with input matching LC ladder technique circuitry to cover the upper band of UWB from 3.1 to 10 GHz. Also, an improved technique of derivative superposition (DS) method is proposed to improve the linearity by using both forward body bias technology, and currentreused. The proposed LNA can operate at reduced supply voltage and power consumption. This configuration provides better input matching, lower noise figure, and more reverse isolation which is vital in LNA design. Complete analytical simulation of the circuit results in frequency of 3.1 GHz to 10 GHz, with 2.44 dB NF MIN , 50Ω input impedance, 13.5dB peak power gain (S 21), high reverse isolation (S 12)-50 dB,-15dB input matching (S 11) and-10dB output matching (S 22), while dissipating as low power as1.5mW low supply voltage of 0.6 V.