Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers

Krishna, K. Murali; Sailaja, M.

doi:10.1007/s10836-014-5432-1

Cited by 13 publications

(3 citation statements)

References 12 publications

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“…Such advancements have significantly contributed to the scalability and effectiveness of LBIST modules in modern integrated circuits. These advancements contribute considerably to the scalability and effectiveness of LBIST modules in modern integrated circuits [1][2][3][24][25].…”

Section: Literature Reviewmentioning

confidence: 99%

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Ramakrishna S , Rajashekhar B Shettar

2024

jes

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This paper presents a novel approach to optimizing power usage in scalable Built-In Self-Test (BIST) controllers. While BIST mechanisms are crucial for maintaining the reliability of digital circuits, they can be excessively power-hungry during testing phases, particularly in applications where energy consumption is a concern. We propose an innovative architecture incorporating reversible logic gates and circuits to overcome this challenge. Reversible logic is renowned for its low power consumption as it retains information. By integrating reversible logic into our architecture, we can significantly reduce power usage during test cycles, making it an ideal solution for scalable systems ranging from 8 to 32 bits. Our trials showed substantial power savings compared to traditional BIST approaches without sacrificing test coverage or efficiency. Our research provides new opportunities to develop energy-efficient testing methods for digital circuits, contributing to broader efforts in sustainable electronics design.

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Section: Literature Reviewmentioning

confidence: 99%

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Ramakrishna S , Rajashekhar B Shettar

2024

jes

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“…PRBSs have an advantageous feature from the computational viewpoint, and they tend to have useful structural properties. These structural properties, binary sequences have many applications; for example, Direct Sequence Spread Spectrum (DSSS), PN generation, Built-in Self Test (BIST), Decryption-Encryption System (DES) and Error detection [8] Error Correction and Detection codes [9] and other applications include Digital Signal Processing, Wireless Communications, Data Integrity check sums, Data Compression, Scrambler/descrambler, Optimized Counters [10]- [12].…”

Section: Test Pattern Generatorsmentioning

confidence: 99%

“…For testing purpose we used adk.atpg library along with non scan netlist generated fron leonarto spectrum given to as shown in Figure 5. Further, TD and test time reduction can be calculated using Equations (9) and (10). Table 4, shown the SA and TD for different lengths N (4 bit to 256 bit) , It can be observed that for each length, find least and most significant bits and applies theorm 1 to 4 to calculate SA and TD values.…”

Section: Table 2 Manual Clock Wise Transition Density Comparisonmentioning

confidence: 99%

An approach to Measure Transition Density of Binary Sequences for X-filling based Test Pattern Generator in Scan based Design

Hussain¹,

Rao²

2018

IJECE

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<span>Switching activity and Transition density computation is an essential stage for dynamic power estimation and testing time reduction. The study of switching activity, transition densities and weighted switching activities of pseudo random binary sequences generated by Linear Feedback shift registers and Feed Forward shift registers plays a crucial role in design approaches of Built-In Self Test, cryptosystems, secure scan designs and other applications. This paper proposed an approach to find transition densities, which plays an important role in choosing of test pattern generator We have analyze conventional and proposed designs using our approache, This work also describes the testing time of benchmark circuits. The outcome of this paper is presented in the form of algorithm, theorems with proofs and analyses table which strongly support the same. The proposed algorithm reduces switching activity and testing time up to 51.56% and 84.61% respectively.</span>

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Design and Analysis of Low-Transition Address Generator

Saravanan

Hailu

Gouse

et al. 2019

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers

Cited by 13 publications

References 12 publications

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

An approach to Measure Transition Density of Binary Sequences for X-filling based Test Pattern Generator in Scan based Design

Design and Analysis of Low-Transition Address Generator

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