2008
DOI: 10.3844/ajassp.2008.312.319
|View full text |Cite
|
Sign up to set email alerts
|

Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System

Abstract: Modulo 2 n +1 adders find great applicability in several applications including RNS implementations. This paper presents a new number system called Carry Save Diminished-one for modulo 2 n +1 addition and a novel addition algorithm for its operands. In this paper, we also present a novel architectures for designing modulo 2 n +1 adders, based on parallel-prefix carry computation units. CMOS implementations reveal the superiority of the resulting adders against previously reported solutions in terms of implemen… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2009
2009
2018
2018

Publication Types

Select...
4
1

Relationship

1
4

Authors

Journals

citations
Cited by 5 publications
(1 citation statement)
references
References 25 publications
0
1
0
Order By: Relevance
“…It has provided some benefits for VLSI implementation. The redundant number systems are used to accelerate addition process in some other number systems such as residue number systems [2,3,4].…”
Section: Introductionmentioning
confidence: 99%
“…It has provided some benefits for VLSI implementation. The redundant number systems are used to accelerate addition process in some other number systems such as residue number systems [2,3,4].…”
Section: Introductionmentioning
confidence: 99%