Low Power Probabilistic Floating Point Multiplier Design

Gupta, Anoop; Mandavalli, Satyam; Mooney, Vincent J.; Ling, Keck Voon; Basu, Arindam; Johan, Henry; Tandianus, Budianto

doi:10.1109/isvlsi.2011.54

Cited by 32 publications

(31 citation statements)

References 8 publications

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“…This area ratio which corresponds to the error detection probability is obtained based on the fact that only duplicated parts and comparators in the new multiplier have error detection capability. Thus, for example, for k equal to 17 to 11850.8 um 2 in this design. It is clear that more error detection probability will be reached if a longer mantissa is used in the proposed design.…”

Section: Resultsmentioning

confidence: 94%

“…Previous reduced-precision or bit truncation schemes [15][16][17][18] focused on reducing the power consumption in the mantissa multiplication block, due to the fact that it consumes the largest amount of power consumption in a floating-point multiplier. In [15], it is examined that how a software-based system can employ the minimal number of bits for mantissa and exponent in the floating-point hardware to reduce the power consumption while maintaining the program's overall accuracy.…”

Section: Related Workmentioning

confidence: 99%

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A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier

Mohajer¹,

Valinataj²

2017

IJMECS

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Abstract-This paper presents a new fault-tolerant architecture for floating-point multipliers in which the fault-tolerance capability is achieved at the cost of output precision reduction. In this approach, to achieve the faulttolerant floating-point multiplier, the hardware cost of the primary design is reduced by output precision reduction. Then, the appropriate redundancy is utilized to provide error detection/correction in such a way that the overall required hardware becomes almost the same as the primary multiplier. The proposed multiplier can tolerate a variety of permanent and transient faults regarding the acceptable reduced precisions in many applications. The implementation results reveal that the 17-bit and 14-bit mantissas are enough to obtain a floating-point multiplier with error detection or error correction, respectively, instead of the 23-bit mantissa in the IEEE-754 standardbased multiplier with a few percent area and power overheads.

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Section: Resultsmentioning

confidence: 94%

Section: Related Workmentioning

confidence: 99%

A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier

Mohajer¹,

Valinataj²

2017

IJMECS

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“…Some methods use approximate computing to come up with low-power designs. These methods are voltage over scaling (VOS) [11,26,45,55], biased VOS (BIVOS) [5,6,13,34,42,44], bit width reduction [15,50,54], cutting lower significant parts [36] and hardware simplification [16,21,36,42,43,59]. Majority of these techniques focused on adders, multipliers and their derivative systems.…”

Section: Related Workmentioning

confidence: 99%

“…1. Since carry out is not calculated for the lower part, ETA has better performance than a precise adder in terms of processing [15]. a Conventional MA, b Approximation 1 obtained by reducing some transistors from conventional MA, c Approximation 2 in which Sum = Cout, d Approximation 3 in which Cout has a more simplified circuit and Sum = Cout, and e Approximation 4 in which Cout = A and sum is calculated as in Approximation 1 speed, power and area consumption.…”

Section: Related Workmentioning

confidence: 99%

Approximate Arithmetic for Low-Power Image Median Filtering

Monajati

Fakhraie

Kabir

2015

Circuits Syst Signal Process

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In applications related to human senses, such as audio and image processing, computations with limited precision are acceptable. In these areas, a digital system can be implemented using approximate computing that works with sufficient precision. In this paper, we present a method to design 2-bit approximate magnitude comparators that are effectively low cost in terms of power, area and speed. We build larger comparators with adjustable error characteristics. Compared to precise one, our approximate comparators can save power and area up to 7-46 % and 10-50 %, respectively. The structures of our comparators and their error characteristics are presented in this paper. We use these comparators to design different approximate image median filters in order to remove salt and pepper noise. Simulation results show that the output quality of these filters is very similar to that of the precise ones so that the degradation is not noticeable. The approximate filters save up to 30 % of power and area while working 18 % faster than the precise ones.

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“…A design of a low power FP multiplier was investigated by Tong et al [10] this design includes truncation of hardware & a reduction of the bit width representation of the FP data. A probable FP multiplier design was given by Gupta et al [11]. as an energy efficient design.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Low Power Inexact Floating Point Adder

Pedraj¹,

Kumar²

2017

IJCA

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Floating-point applications are a growing trend in the FPGA community. In nanoscale integrated circuits design as the demand for mobile computing & higher integration density is increasing power is becoming a very important constraint. Low-power is an imperative requirement for portable multimedia devices employing various signal processing algorithms and architectures. For some applications where error is in tolerable range an inexact circuit offers reduction in both static and dynamic power .In this paper, an inexact floating-point adder is designed by approximating exponent sub tractor and mantissa adder. Related operations such as normalization and rounding are also dealt with in terms of inexact computing. It is then observed that it greatly reduced the power consumption and hence increased the reliability. KeywordsFloating-point adders, low power, high dynamic range image, inexact circuits, error analysis.

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Low Power Probabilistic Floating Point Multiplier Design

Cited by 32 publications

References 8 publications

A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier

A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier

Approximate Arithmetic for Low-Power Image Median Filtering

Design and Implementation of Low Power Inexact Floating Point Adder

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