Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence

Abstract

This paper proposes low power optimization using a modified swarm intelligence algorithm for the scenariostransistor sizing based static power reduction and low power standard cell generation for approximate computing. In these scenarios, we explore a lower abstraction level and see how standard cells can be tuned to a power-delay-quality optimal point. For transistor sizing, the algorithm considers fabrication process parameter variations (for ±3σ design) in addition to a wide range of temperature (-55 o C to 125 o C) and supply voltage (±10%) variations to yield PVT aware robust sizing solutions. The approach has been applied on numerous single and multistage circuits (including ISCAS benchmarks) while proposing a dual sizing solution for non-critical and critical path cells. For approximate systems, we present algorithm-generated full adder designs for speech processing systems. The designs vary in terms of accuracy and power. Results show leakage reductions up to 58.2% for conventional and 66.8% with approximation designs for 22nm metal gate high-K (MGK) technology cells.

A Machine Learning Based Reliability Analysis of Negative Bias Temperature Instability (NBTI) Compliant Design for Ultra Large Scale Digital Integrated Circuit

“…When it comes to replacing the CMOS technology used in electrical circuits, MGK is one of the options. With a shorter propagation delay and less power loss, an MGK transistor is able to perform better [1]- [2]. In reliability variations, the performance of the circuit diminishes over some time period, and this impact is also known as the aging effect [3]- [4].…”