Low power reconfigurable FP-FFT core with an array of folded DA butterflies

Abstract

A variable length (32~2,048), low power, floating point fast Fourier transform (FP-FFT) processor is designed and implemented using energy-efficient butterfly elements. The butterfly elements are implemented using distributed arithmetic (DA) algorithm that eliminates the power-consuming complex multipliers. The FFT computations are scheduled in a quasi-parallel mode with an array of 16 butterflies. The nodes of the data flow graph (DFG) of the FFT are folded to these 16 butterflies for any value of N by the control unit. Register minimization is also applied after folding to decrease the number of scratch pad registers to (log 2 N − 1) × 16. The real and imaginary parts of the samples are represented by 32-bit single-precision floating point notation to achieve high precision in the results. Thus, each sample is represented using 64 bits. Twiddle factor ROM size is reduced by 25% using the symmetry of the twiddle factors. Reconfigurability based on the sample size is achieved by the control unit. This distributed floating point arithmetic (DFPA)-based design of FFT processor implemented in 45-nm process occupies an area of 0.973 mm 2 and dissipates a power of 68 mW at an operating frequency of 100 MHz. When compared with FFT processor designed in the same technology with multiplier-based butterflies, this design shows 33% less area and 38% less power. The throughput for 2,048-point FFT is 222 KS/s and the energy spent per FFT is 7.4 to 14 nJ for 64 to 2,048 points being one among the most energy-efficient FFT processors.

A Streaming Data Processing Architecture Based on Lookup Tables

“…The clock frequency of LSDP is set to 50 MHz. Under the same FFT size and clock frequency, the proposed architecture has certain advantages in terms of throughput, computing time, and energy consumption compared to [21], with a power of only 3.53 mW. Due to the high parallelism of computation in FPGA, it has certain advantages in computing speed but consumes more energy than LSDP.…”

Number Systems for Deep Neural Network Architectures

“…However, this approach introduces approximation and low precision to the FFT computations. In contrast, some researchers have opted for singleprecision FP (32-bit) representations to enhance FFT accuracy [26], [32]- [34]. Although the use of FP arithmetic reduces FFT errors, it comes at the cost of reduced speed, increased power consumption, and greater chip silicon requirements [26].…”

“…Hence, the direct comparison between these processors is not fair. For fair comparison, We use normalized metrics, normalized area, and normalized power, similar to the ones proposed in [26], [34] that consider these variations. The formulae that calculate normalized area, normalized power, and normalized energy metrics with respect to our implementation are presented in ( 7), (8), and (9), respectively.…”

Improving Energy Efficiency of OFDM Using Adaptive Precision Reconfigurable FFT

“…Although there are very few approaches focusing on the floating-point FFT [2,38], most of the energy-efficient designs concentrate on the fixed-point FFT, mostly due to its less complexity and lower power dissipation. In the multimode systems, it seems to be more effective to have a reconfigurable FFT unit in order to achieve the required word-length, accuracy, speed and consequently, more efficient energy consumption.…”