Low‐power sample and hold circuits using current conveyor analogue switches

Abstract

This study presents low-power sample and hold (S/H) circuits using second-generation current conveyor (CCII). Unlike previous S/H circuits, switch of the proposed S/H circuits can be obtained using CCII which works as current conveyor analogue switch (CCAS). The state of CCAS is controlled by sampling pulse that can be applied via its bias current source. The proposed S/H circuits offer low-power consumption, high-speed and absent from non-overlapping clock signal requirements. Three configurations of S/H circuit are proposed, namely single-ended S/H, differential S/H and serial-to-parallel S/H circuits. The proposed S/H circuits have been simulated using 0.18 µm complementary metal oxide semiconductor (CMOS) process from Taiwan semiconductor manufacturing company (TSMC). The simulation results are used to confirm the workability of the proposed structures.

A 1 V, 10 KS/S, 71.2 db SNDR current-mode CMOS sample-and-hold circuit for high-speed wireless communication applications

“…The core of S/H needs a bias current source, for the sake of decreasing offset resulting from supply voltage, the current source which has a characteristic of independent-supply is introduced and is shown in Fig. 6 [18].…”

“…The circuit combined the negative feedback and compression I-V characteristics of class AB weak inverters to achieve low switching error, high signal-tonoise ratio and high dynamic range at low voltage and low current consumption. In 2018, Kumngern et al [18] designed a low-power S/H circuit using the second generation current transporter (CCII). Different from the previous S/H circuit, the proposed S/H circuit could use CCII as the current transfer analog switch (CCAS).…”