Low power SC CMFB folded cascode OTA optimization

Daoud, Houda; Bennour, S.; BenSalem, S.; Loulou, Mourad

doi:10.1109/icecs.2008.4674917

Cited by 14 publications

(2 citation statements)

References 7 publications

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“…Therefore presence of a common mode feedback circuit ensures that the output does not drift away with temperature or process variations and are more crucial while designing for high resolution. Since non overlapping phase clocks are available for the SHA, the main stage amplifier uses a switch capacitor CMFB [16] [17] (as shown in Fig.5) which has the additional advantage of low power consumption and higher accuracy [6].…”

Section: Common Mode Feedback Circuit Designmentioning

confidence: 99%

Design of sample and hold for 16 bit 5 Ms/S pipeline analog to digital converter

Mohapatra

Gupta

Mohapatra

et al. 2014

2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking

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This work presents the design and simulation of a low power CMOS Sample and Hold OTA for a 16bit, 5Ms/S pipelined ADC. The designing of high precision amplifiers is challenging in modern CMOS process. It drives ADC design methodology towards advance calibration approaches and compromised with low SNR. This paper deals with advance design techniques for High gain like triple cascode and achieves a DC gain of 132 dB and 68 MHz unity gain bandwidth with a phase margin of 88 degrees while driving the 16pf load of the first stage. Transient response of Charge Redistribution SHA shows settling accuracy of 15µV in 66 nanoseconds while consuming 20mW power. Switched capacitor CMFB has been implemented for the gain boosting amplifiers and main stage amplifier respectively. The design has been implemented in UMC 0.18µm technology. Design methodology for high gain and better settling performance at low power are also discussed in detail.

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Section: Common Mode Feedback Circuit Designmentioning

confidence: 99%

Design of sample and hold for 16 bit 5 Ms/S pipeline analog to digital converter

Mohapatra

Gupta

Mohapatra

et al. 2014

2014 2nd International Conference on Emerging Technology Trends in Electronics, Communication and Networking

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“…This enabled us to reach the most suitable operating speed over power consumption ratio. The OTA parameters were set according to a design sample developed in [17]. The simulated parame-ters of the OTA are summarized in Table 4 and reported on Simplorer OTA model.…”

Section: Operational Tranconductance Amplifier (Ota) Parametersmentioning

confidence: 99%

Behavioral Modeling and Simulation of Cascade Multibit ΣΔ Modulator for Multistandard Radio Receiver

Zouari¹,

Daoud²,

Loulou³

et al. 2013

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In this paper, a cascade Sigma-Delta (ΣΔ) Analog to Digital Converter (ADC) for multistandard radio receiver was presented. This converter is supposed to be able to support GSM, UMTS, Wifi and WiMAX communication standards. The Sigma-Delta modulator makes use of 4 bit quantizer and Data-Weighted-Averaging (DWA) technique to attain high linearity over a wide bandwidth. A top-down design methodology was adopted to provide a reliable tool for the design of reconfigurable high-speed ΣΔMs. VHDL-AMS language was used to model the analog and mixed parts of the selected 2-1-1 cascade ΣΔ converter and to verify their reconfiguration parameters based on behavioural simulation. This multistandard architecture was high level sized to adapt the modulator performance to the different standards requirements. The effects of circuit non-idealities on the modulator performance were modeled and analyzed in VHDLAMS to extract the required circuit parameters.

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