Low Power Sram Design Using Block Partitioning

Abstract

Technology scaling results in significant increase of leakage currents in MOS devices due to which power consumption in Nano scale devices increases. As memory accounts for the largest share of power consumption, thus there is need to design such a memory which will consume less power. Through this paper, we propose a systematic approach by Block partitioning which provides a methodology for reducing the dynamic power consumption of SRAM (static random access memory). Dynamic power dissipation in memory is due to charging/discharging of long capacitive lines (bit line and world line). So by block partitioning our goal is to reduce length of world line as