Low power synchronous buffer based Queue for 3D MPSoC

Kathuria, Jagrit; Chhabra, Aakriti; Kaur, Gagandeep; Chadha, Raman

doi:10.1109/wict.2011.6141345

Cited by 5 publications

(3 citation statements)

References 10 publications

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“…There are two types of first-in-first-out design and architecture: series and parallel [6], [13], [11], [1], [14], [15]. First In First Out serial works like shift registers; the first generation is first in first out.…”

Section: Input Port Design Techniquesmentioning

confidence: 99%

Network-on-chip router input port architectures

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jamali

Màsdàrí

et al. 2022

Preprint

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With the increase in the number of processing cores on a chip, a highly efficient and scalable structure such as a network on a chip was proposed. Network-on-chip is a technology presented to solve the limitations of system-on-chip that includes a set of multiprocessors. In network-on-chip systems, delay in communication and reaching the ideal speed is one of the concerns of academic and industrial researchers today. Although network-on-chip offers a favorable solution to reduce the problem of the long delay of wires compared to traditional structures, communication delay is still a challenge. In this article, the various types of network router input ports architecture on the chip are reviewed and the operational comparison and evaluation of the technologies proposed in this field are mentioned.

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Section: Input Port Design Techniquesmentioning

confidence: 99%

Network-on-chip router input port architectures

Fard

jamali

Màsdàrí

et al. 2022

Preprint

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“…There are two types of FIFO designs and architectures: serial and parallel [4,7,13,26,27,28,29]. The serial FIFO (such as shift register) that works by fall-through principle has been the first FIFO generation as shown in Figure 2.1.…”

Section: Serial and Parallel Fifo Architecturementioning

confidence: 99%

Virtual channel organization and arbitration for network on chip router architecure

Gharan¹

2021

Preprint

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The advent of Multi-Processor Systems-on-Chip (MPSoC) has emphasized the importance of on-chip communication infrastructures. Network on Chip (NoC) has emerged as a state of the art paradigm for efficient on-chip communication. Among the various components employed in NoC routers, Virtual Channel (VC) plays an important role in the performance and hardware requirements of an NoC system. The VC mechanism enables the multiplexing and buffering of several packets to travel over a single physical channel concurrently. VC arbitration (or arbiter) is another critical organization component of a router that has significant impact on the efficiency of an NoC system. Arbiter performs arbitration among the group of VCs that are competing for a single resource (e.g. output-port). In this dissertation, we propose novel approaches for dynamic VC flow control mechanism and VC arbitration. The first two approaches are based on the adaptivity of VCs in the router input-port that improves the efficiency of NoC system. In both of techniques, the input-port comprises of a centralized buffer whose slots are dynamically allocated to VCs according to a real-time traffic situation. The performance improvement is achieved by utilizing multiple virtual channels with minimal buffer resources. The VC arbitration approach is based on an efficient and fast arbiter that functions upon the index of its input-ports (or VC requests). The architecture of arbiter scales with the Log2 of the number of inputs where a conventional round robin arbiter scales with the number of inputs. The index based behavior and the architecture of our arbiter leads to lower power consumption and chip area. This dissertation presents the organizations and micro-architectures of NoC routers. We have employed SystemVerilog at the micro-architectural level design and modeling of NoC components. We employ three CAD platforms namely ModelSim, Quartus (FPGA) and Synopsys (ASIC level) to design, simulate and implement our router based NoCs. The simulation results support the theoretical concepts of our proposed VC organization and arbitration approaches. We have also implemented and conducted simulation and modeling experiments for conventional VC organization and arbitration models. The experimental results verify the efficiency of our proposed models in terms of power, area and performance in different NoC configurations.

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“…However, in terms of architecture, FIFO is mostly referred to serial or parallel FIFOs, and the queue is referred FCFS based buffer that also comprises FIFO buffers too. There are two types of FIFO designs and architectural schemes: serial and parallel [2,12,13,14,15,16,17,18,19]. The serial http://dx.doi.org/10.12785/ijcds/040102 http://journals.uob.edu.bh FIFO (such as shift register) that works by fall-through principle is the first generation FIFO.…”

Section: A Fifo Buffersmentioning

confidence: 99%

Packet-based Adaptive Virtual Channel Configuration for NoC Systems

Gharan¹

2015

IJCDS

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The escalating numbers of on-chip processing cores necessitate the introduction of a high performance and scalable communication backbone. In respond to this, Network on Chip (NoC) systems are introduced to play an important role in determining the performance and power of the entire chip. Specifically, Packet-based NoC is known as the most viable communication solution for the multi-core SoC of the future. In NoC design, the buffering organization directs the control of data flow as well as facilitates the use of Virtual Channels (VC). In terms of buffering, the VC mechanism is categorized into static and dynamic models. In dynamic VC mechanism, VCs employ a variable number of buffer slots according to the on-chip traffic. This feature of dynamic VC mechanism encourages us to introduce the Packet Based Virtual Channel (PBVC) approach. The idea is that a VC is reserved when a packet comes in a router, and released when the packet leaves the router. This prevents a VC to hold more than one packet that subsequently removes the Head-of-Line (HOL) blocking in NoCs. Our proposed technique is more suitable for dynamically allocated multi-queue (DAMQ) schemes. In these schemes, an input or output port comprises a centralized buffer whose slots are dynamically allocated to VCs in real-time and according to the traffic conditions. We introduce the architectural and structural details of our DAMQ buffer organization as well as the hardware that our approach imposes. The simulation results support the theoretical concepts of our proposed technique. The results of the hardware requirements for the proposed model are compared with the conventional models. The experimental results show that PBVC can improve the network latency by 40% and the network throughput by 23% on average as compared to the conventional designs for specific high HOL traffic.

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Low power synchronous buffer based Queue for 3D MPSoC

Cited by 5 publications

References 10 publications

Network-on-chip router input port architectures

Network-on-chip router input port architectures

Virtual channel organization and arbitration for network on chip router architecure

Packet-based Adaptive Virtual Channel Configuration for NoC Systems

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