Low-Power Ternary Content-Addressable Memory Using Power Reduction of Match-Line and Search-Line

Abstract

Abstract:The challenge to solve in large capacity ternary content addressable memory (TCAM) is the large power consumption of search-line and match-line. In this paper, we propose a circuit that uses match-line selectivecharging scheme and low-swing search-line scheme simultaneously to reduce power consumption of search-line and match-line which occupies a large ratio in power consumption of TCAM. The circuit was verified by Hspice simulation using a 1.8V supply voltage in a CMOS 0.18 um CMOS process. The proposed 128x128 bit TCAM shows 45.4% power savings in match-line and 74.7% power savings in search-line compared to the conventional precharge high scheme in search cycle. Also, the minimum search cycle time is 3 ns (333MHz).

Design and Analysis of Power‐Efficient Quasi‐Adiabatic Ternary Content Addressable Memory (QATCAM)

“…Various low‐power techniques are employed for combating high‐power consumption in high‐speed TCAM cells. Though many low‐power techniques have been proposed to reduce power in ML and search line switching [5–8], the principle of adiabatic logic (AL) works well in the reduction of power dissipation by using the energy recovery process proposed in [9, 10]. The use of AL in the design of binary CAM cells [11–13] has resulted in better power savings.…”