Low-Power Test Pattern Generation

Wen, Xiaoqing; Wang, Seongmoon

doi:10.1007/978-1-4419-0928-2_3

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Requirements In Lsi Testing1

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2010

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“…Both of them are related to test power (power dissipated in test mode), which is often several times higher than functional power. Excessive test power has become a major test safety issue, especially in at-speed scan testing for low-power devices [5,[7][8][9].…”

Section: Requirements In Lsi Testingmentioning

confidence: 99%

CAT (Critical-Area-Targeted): A New Paradigm for Reducing Yield Loss Risk in At-Speed Scan Testing

et al. 2010

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At-speed scan testing is essential in guaranteeing LSI chip quality in the deep-submicron era; however, chip/package damage, yield loss, and reliability degradation may occur in at-speed scan testing due to excessive test power, which can be several times higher than functional power. This problem is especially severe for low-power devices. In this paper, the background of the test power problem is reviewed, and the characteristics of two different types of test power (shift and capture) are highlighted. Then, a general strategy for test power reduction is described. After that, information on a novel CAT (critical-area-targeted) technique for tackling the more challenging problem of capture power reduction is provided. This unique and sophisticated technique can effectively reduces launch switching activity in a pinpoint manner by targeting at areas around long sensitized paths (called critical areas). Evaluation results on industrial circuits demonstrate the need for such CAT techniques.

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Section: Requirements In Lsi Testingmentioning

confidence: 99%