Low power Wallace multiplier design based on wide counters

Abstract

Multiplication is one of the most basic arithmetic operations. It is used in digital applications, central processing units, and digital signal processors. In most systems, the multiplier lies within the critical path and hence, due to probability and reliability issues, the power consumption of the multiplier has become very important. Moreover, as chips shrink and their power densities increase, power is becoming a major concern for chip designers. The ever increasing demand for portable applications with their limited battery lifetime indicates that power considerations should be a center stone in today's designs and the future's designs. Thus, all this has motivated us to provide a novel circuit design technique for a low power multiplier without compromising the multiplier's speed.This paper presents a new power aware multiplier design based on Wallace tree structure. A new algorithm is proposed using high-order counters to meet the power constraints imposed by mobility and shrinking technology. Commonly used multipliers of widths 8, 16, and 32 bits are designed based on the proposed algorithm. The new approach has succeeded in reducing the total number of gates used in the multiplier tree. Simulations on Altera's Quartus-II FPGA simulator showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multiplier's size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power-delay product in 32-bit multipliers.

Hardware design and modeling of lightweight block ciphers for secure communications

“…Implementations were designed and analyzed based on advanced design flow similar to design flows used in other research works such as [36][37][38][39][40]. The design flow is summarized as follows:…”

“…VCD files are fed to Quartus-II tool to compute design power. This technique is commonly used in research works such as [36][37][38][39][40] and [34]. The reported power is mainly the core dynamic power which includes combinational logic power, clock tree power and register power.…”

Asymmetric large size multipliers with optimised FPGA resource utilisation

“…Different tiling techniques were used to decompose the large size multipliers, which efficiently reduce the use of multiplier blocks but are less flexible. In [11], a new algorithm was proposed to construct a low-power multiplier based on the Wallace tree. Among other things, it tackles the lengthy interconnects in Wallace tree multipliers and reduces the power dissipation and the gate usage through the use of high-order counters.…”

Simplified carry save adder‐based array multiplier scheme and circuits design

“…Multipliers are used in many digital systems available today especially in digital signal processors [1]. The design and implementation approaches of multipliers contribute substantially to the area, speed, and power consumption of computational intensive VLSI systems [2][3][4].…”