Low-power weighted pseudo-random BIST using special scan cells

Abstract

In this paper, a technique for weighted pseudo-random builtin self-test (BIST) of VLSI circuits is proposed, which uses special scan cells and a new weight selection algorithm to achieve low power dissipation. It is based on weighted pseudo-random scan testing in which only 3 weight values are used -2 fixed values (0 or 1) and 1 random value (0.5). A new weight selection algorithm is used to select a set of weights that achieves high fault coverage while reducing power. The idea is to minimize power by careful selection of the set of scan cells having fixed values (0 or 1) in order to reduce switching activity. To implement this in hardware, a new scan cell design is proposed that can do scan and capture in the normal mode as well as fixed-bit mode. The new scan cell hardware increases the area of a typical circuit by less than 4%, but reduces power by as much as 96%, as indicated in experiments performed on benchmark circuits.

A Method for Weight Set Compaction in Power Aware Multiple Weighted Random BIST

“…Low transition test pattern generation method has been proposed in reference (5), and a 3-weight weighted random BIST method and scan-reordering have been proposed in reference (6). Weighted random BIST scheme with special scan cell deign for bit fixing has been proposed in reference (7). In our previous study, we exploited fault clustering using circuit topology to control power consumption (14) .…”