Low‐quiescent‐current flexible mode buck–boost converter

Cheng, Lixin; Lai, Xiaojun; Shi, Lei

doi:10.1049/iet-pel.2014.0888

Cited by 8 publications

(3 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Some test results of the proposed converter appear not as better as those of the earlier papers when only taking the absolute value into account. However, considering the fact that the maximum load current is considerably greater in this proposed converter than that in [25][26][27], it still has lower overshoot/undershoot voltages, and faster settling time. Fig.…”

Section: Resultsmentioning

confidence: 97%

Fixed‐frequency adaptive on‐time buck converter with ramp compensation

Lai

et al. 2016

IET Power Electronics

View full text Add to dashboard Cite

This study presents a fixed-frequency adaptive on-time buck converter with adaptive ramp compensation internally, which uses valley current-mode control. The on-time is obtained by feed forwarding input voltage and output voltage, which is easy to implement. The control method provides fast transient response, wide duty ratio and high efficiency for both heavy and light load. In a traditional adaptive on-time buck converter, the output voltage ripple determines the moment when the main power metal oxide semiconductor field effect transistor is being turned on. Different from that way, this study proposes a new way by which the valley current flowing through the inductor determines the moment. This avoids the problem induced by insufficient output ripple when a low equivalent series resistance capacitor like ceramic output capacitor is used. An adequate and simple ramp compensation circuit is proposed to optimise its jitter performance for wide duty ratio applications.

show abstract

Section: Resultsmentioning

confidence: 97%

Fixed‐frequency adaptive on‐time buck converter with ramp compensation

Lai

et al. 2016

IET Power Electronics

View full text Add to dashboard Cite

show abstract

“…In the next sub-section, the proposed work will be presented and analyzed in greater detail. At the same time, there are other DC-DC converters which can provide a wide load range with good efficiency while consuming very low quiescent current, which will no doubt be the major power consumption in sensing or low-load mode [63][64][65][66][67][68][69][70].…”

Section: Voltage Level Shiftermentioning

confidence: 99%

A DC-DC Converter with Switched-Capacitor Delay Deadtime Controller and Enhanced Unbalanced-Input Pair Zero-Current Detector to Boost Power Efficiency

Kok,

Tang,

Teo

et al. 2024

Electronics

View full text Add to dashboard Cite

This proposed work introduces a DC-DC converter with Switched-Capacitor Delay Deadtime Controller (SCD-DTC), Digitally Controlled Start-Up Block (DC-SUB), and Enhanced Unbalanced-Input Pair Zero-Current Detector (EUIP-ZCD) that helps to improve the overall power efficiency. It also introduces the discussion of key signal waveforms and the two major optimization flowcharts. This proposed DC-DC converter can simultaneously achieve optimized deadtime (body diode conduction < 3 ns) and almost fully eliminate the phenomenon of reverse inductor current (RIC). Furthermore, it also shows that it can achieve a well-regulated output voltage of 1.8 V with <0.01% of output ripple riding on it. All the post-layout simulation results are carried out using 0.18 µm 1P6M CMOS process using Cadence Virtuoso Spectre Circuit Simulator. The silicon chip area of our proposed work (including the output pad frame) is 1.44 mm2. The chip fabrication was sent out in January 2024 and the return of the measurement dies is expected in March 2024. The post-layout simulation results will no doubt closely resemble the measurement results since the proposed work is mostly controlled by digital blocks.

show abstract

“…However, this converter is implemented in 0.18 um BCD technology, which is too costly for us to handle, and the power efficiency seems to degrade drastically under very light load conditions (<100 µA). At the same time, there are other converters which are capable of providing a wide load range with good efficiency and consuming a very low quiescent current, which will no doubt be the major power consumption in sensing or low load mode [17,18,[43][44][45][46][47][48].…”

Section: Future Workmentioning

confidence: 99%

Designing a Twin Frequency Control DC-DC Buck Converter Using Accurate Load Current Sensing Technique

Kok,

Siek

2023

Electronics

View full text Add to dashboard Cite

In this paper, a buck DC-DC converter with the proposed twin frequency control scheme (TFCS) and accurate load current sensing (ALCS) was designed and implemented with 0.18 µm CMOS technology for a supply voltage ranging from 2.0 to 3.0 V, which is compatible with state-of-the-art batteries (NiCd/NiMH: 1.1–2 V, Li-Ion: 2.5–4.2 V). The proposed converter yields a peak efficiency of about 92.7% with a load current of 30 mA. Furthermore, it only occupies a silicon area of 1.3 mm2. The proposed buck converter is dedicated for smartphone applications whereby it spends most of its time in idle, low load conditions.

show abstract

Low‐quiescent‐current flexible mode buck–boost converter

Cited by 8 publications

References 27 publications

Fixed‐frequency adaptive on‐time buck converter with ramp compensation

Fixed‐frequency adaptive on‐time buck converter with ramp compensation

A DC-DC Converter with Switched-Capacitor Delay Deadtime Controller and Enhanced Unbalanced-Input Pair Zero-Current Detector to Boost Power Efficiency

Designing a Twin Frequency Control DC-DC Buck Converter Using Accurate Load Current Sensing Technique

Contact Info

Product

Resources

About