Low Residual Stress and High Performance Dielectric for WLP (Wafer Level Packaging) Applications

Abstract

The advanced packaging application space continues to evolve as mobile devices pack more and more features into a limited space. This feature concentration is causing a deviation from the conventional shrinkage pathway predicted by Moore's law which, in turn, requires dielectric materials with ever more rigid thermal, chemical, and mechanical properties to meet the challenging requirements of next generation packages such as TSV and 3D chip stacking. One such challenge is the thinner substrates required for vertical integration in TSV and 3D packages. Cured dielectrics impart stress onto the underlying substrate and this wafer bow will only magnify with thinner substrates. Designing photodielectrics with inherently lower residual stress will greatly aide in the development of materials to meet future advanced packaging needs. This presentation will outline the development of a new photodielectric material that builds upon the excellent thermal, electrical, and chemical stability of BCB-based materials while providing a significant reduction in residual stress.