Low resistance wiring and 2Xnm void free fill with CVD Ruthenium liner and DirectSeed&lt;sup&gt;TM&lt;/sup&gt; copper

Rullan, Jonathan; Ishizaka, Tadahiro; Cerio, Frank; Mizuno, Shigeru; Mizusawa, Yasushi; Ponnuswamy, Thomas; Reid, Jonathan D.; McKerrow, Andrew J.; Yang, Chih‐Chao

doi:10.1109/iitc.2010.5510705

Cited by 11 publications

(8 citation statements)

References 2 publications

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“…Ti barrier layers can be used instead of Ta to reduce cost [83,84]. Ru is of interest as a replacement for Ta because it has lower resistivity than Ta (which allows thinning or elimination of the Cu seed layer) and because Cu has better wettability on Ru compared to Ta [85][86][87][88]. However, Cu wetting on TiN is poor, so a thin Ti layer is required on top of the TiN for good wetting of Cu [84].…”

Section: Metallizationmentioning

confidence: 99%

Process Technology for Copper Interconnects

Gambino

2012

Handbook of Thin Film Deposition

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Section: Metallizationmentioning

confidence: 99%

Process Technology for Copper Interconnects

Gambino

2012

Handbook of Thin Film Deposition

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“…Against this backdrop, the main focus of the chapter lies on the Cu/TaO x /Ru device. As already mentioned, Ru is a good candidate to replace Pt and has been already deployed in the earlier CMOS BEOL technology nodes supplanting Ta or TaN as the liner material [26,27]. Ru is ca.…”

Section: Introductionmentioning

confidence: 99%

Inertness and Other Properties of Thin Ruthenium Electrodes in ReRAM Applications

Chakraborty¹,

Al‐Mamun²,

Orłowski³

2023

Ruthenium - Materials Properties, Device Characterizations, and Advanced Applications

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Building nonvolatile memory such as resistive random access memory (ReRAM) directly into a CMOS backend (BEOL) would reduce latency in connectivity-constrained devices and reduce chip’s footprint by stacking non-volatile memory (NVM) on top of the logic circuits. This co-integration is facilitated by a broad commonality between ReRAM and BEOL as both rely on the same basic metal–insulator–metal (MIM) structure. One good candidate for a ReRAM cell is the Cu/TaOx/Pt device. As platinum (Pt) is not an economic choice, a BEOL-compatible replacement is desirable. A good candidate to replace Pt electrode is ruthenium (Ru), currently being used as a liner/diffusion barrier in sub-15 nm technology nodes and soon to supplant tungsten as via, and copper (Cu) as interconnect materials. We report on extensive characterization of a Cu/TaOx/Ru device and compare its performance and reliability with extant ReRAM devices. Against the background of well-characterized non-Ru ReRAM devices, Cu/TaOx/Ru cell constitutes a micro-laboratory for testing a wide range of Ru properties with the Cu nanofilament as a probe. Since the temperature of the cell can be controlled internally from 27°C to ∼1100°C, thin Ru layers can be subjected to much more comprehensive tests than it is possible in the interconnect MIM structures and reveal and confirm interesting material properties, including the impact of embedment.

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“…A conducting seed is a prerequisite for the electrodeposition of Cu, which is so far the preferred method for TSV metallization. Ru has been widely considered as a seed layer for Cu electrodeposition in high aspect ratio BEOL and 3DI structures [1,2], with added advantage due to its barrier properties. To reduce cost of ownership, a thin Ru seed layer is desirable, which in turn results in an increased challenge to Cu electrodeposition due to the higher electrical resistance of the thin Ru layer.…”

Section: Introductionmentioning

confidence: 99%

Direct Cu plating of high aspect ratio through silicon vias (TSVs) with Ru seed on 300 mm wafer

Wafula

Pattanaik

Enloe

et al. 2014

IEEE International Interconnect Technology Conference

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In this paper, physical and electrical results of full wafer direct Cu plating of 2×40 µm TSVs with thin Ru seed are presented. Physical vapor deposition of about 100 nm Cu in the field is shown to improve plating non-uniformity across the structured wafer. TSV plating using Atotech's TSV III chemistry results in bottom-up growth with strong TSV sidewall suppression and void free TSV fill. Early results for in-line electrical test and voltage ramp dielectric breakdown reliability testing are discussed. INTRODUCTIONHigh-aspect ratio TSVs are desirable for 3D-IC integration with increased device density and smaller keepout zones. Good step coverage of thin film barrier and seed for such TSVs becomes increasingly challenging when TSVs exceed a depth to diameter ratio of 15:1. Traditional physical vapor deposition (PVD) techniques fail to yield uniform coverage. Hence chemical vapor deposition (CVD) or atomic layer deposition (ALD) based barrier and seed layers have been adopted. A conducting seed is a prerequisite for the electrodeposition of Cu, which is so far the preferred method for TSV metallization. Ru has been widely considered as a seed layer for Cu electrodeposition in high aspect ratio BEOL and 3DI structures [1, 2], with added advantage due to its barrier properties. To reduce cost of ownership, a thin Ru seed layer is desirable, which in turn results in an increased challenge to Cu electrodeposition due to the higher electrical resistance of the thin Ru layer.In this report, a study of electroplating high aspect ratio TSVs (depth to diameter aspect ratio of 20:1) with Ru seed layer on 300 mm wafers is presented. A field-only PVD copper film of optimized thickness is used to demonstrate void-free bottom-up TSV filling, mitigating the terminal effect in plating across the wafer. This study also presents TSV in-line electrical test and early reliability results.

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Low resistance wiring and 2Xnm void free fill with CVD Ruthenium liner and DirectSeed<sup>TM</sup> copper

Cited by 11 publications

References 2 publications

Process Technology for Copper Interconnects

Process Technology for Copper Interconnects

Inertness and Other Properties of Thin Ruthenium Electrodes in ReRAM Applications

Direct Cu plating of high aspect ratio through silicon vias (TSVs) with Ru seed on 300 mm wafer

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