2016
DOI: 10.1049/el.2016.2391
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Low Ron and high robustness ESD protection design for low‐voltage power clamp application

Abstract: An electrostatic discharge (ESD) protection circuit with novel structure based on a silicon-controlled rectifier (SCR) is proposed for 5 V ESD protection of integrated circuits. The proposed ESD protection circuit has large current driving capacity due to its low on-resistance and high ESD robustness in comparison with the conventional SCRbased ESD protection circuit. The conventional SCR-based ESD protection circuit and the proposed ESD protection circuit were fabricated using a 0.18 µm bipolar CMOS-double di… Show more

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Cited by 12 publications
(6 citation statements)
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“…The Figure 8 shows the cross section and layout of the proposed ESD protection circuit. As a structural feature of the conventional low-Ron silicon-controlled rectifier (LRSCR), which is the base of the proposed ESD protection circuit structure, by inserting the grounded gate N-MOS (GGNMOS) structure into the conventional SCR structure, an avalanche breakdown happens in the N+ bridge and P-Well regions to lower the trigger voltage [15,16]. By adding P-well and P+ implant regions to the anode region, an additional parasitic PNP bipolar transistor (Qpnp2) is operated, rather than the conventional SCR [17].…”
Section: Ldo Regulator Circuit Configuration With Embedded Esd Protec...mentioning
confidence: 99%
“…The Figure 8 shows the cross section and layout of the proposed ESD protection circuit. As a structural feature of the conventional low-Ron silicon-controlled rectifier (LRSCR), which is the base of the proposed ESD protection circuit structure, by inserting the grounded gate N-MOS (GGNMOS) structure into the conventional SCR structure, an avalanche breakdown happens in the N+ bridge and P-Well regions to lower the trigger voltage [15,16]. By adding P-well and P+ implant regions to the anode region, an additional parasitic PNP bipolar transistor (Qpnp2) is operated, rather than the conventional SCR [17].…”
Section: Ldo Regulator Circuit Configuration With Embedded Esd Protec...mentioning
confidence: 99%
“…The turned‐on NPN parasitic bipolar transistor supplies a base current to the PNP1 and PNP2, and both the PNP transistor and one NPN transistor are turned on. As a result, the proposed ESD protection circuit has a high holding voltage because of its low positive feedback current gain [4, 5].…”
Section: Proposed Esd Protection Circuit Using Penta‐well Structurementioning
confidence: 99%
“…Therefore, the width of the space charge region increases to the direction of the N-well, and then the maximum electric field where the avalanche breakdown occurs is reduced, which in turn causes an increase in the breakdown voltage. A formula between the depletion layer and the maximum electric field is shown as follows [11], In this case, the design variable L2 has a length of 0 um. Where Vbi indicates the potential barrier, VR is the applied reverse bias, and W is a width of the space charge region.…”
Section: Tlp Measurementmentioning
confidence: 99%