Low Source/Drain Contact Resistance for AlGaN/GaN HEMTs with High Al Concentration and Si-HP [111] Substrate

Abstract

An optimized fabrication process of ohmic contacts is proposed to reduce the source/drain access resistance (R C ) and enhance DC/RF performance of AlGaN/GaN HEMTs with a high Al concentration. We show that source/drain R C can be considerably lowered by (i) optimally etching into the barrier layer using Ar + ion beam, and by (ii) forming recessed contact metallization using an optimized Ti/Al/Ni/Au (12 nm/200 nm/40 nm/100 nm) multilayers. We found that a low R C of ∼0.3 .mm can be achieved by etching closer to the 2-Dimensional Electron Gas (2DEG) at an optimum etching depth, 75% of the barrier thickness, followed by a rapid thermal annealing at 850 • C. This is due to the very small distance between the alloy and the 2DEG (higher electric field) as shown by 2D AlGaN/GaN High Electron Mobility Transistors (HEMTs) are significantly beneficial to the semiconductor device industry. They have the potential to replace Si in a range of high-power and high-frequency applications due to the wide bandgap, high electron saturation velocity, good thermal conductivity and high piezoelectricity of III-Nitrides materials.1-4 To fully benefit from the aforementioned material properties, reduction of extrinsic source and drain access resistances (R C ) of AlGaN/GaN HEMTs is essential to enhance their DC/RF performance. To achieve this, several methodologies have been previously proposed.5-9 Firstly, implanting Si into the AlGaN barrier is known to reduce ohmic contact, R C . However, annealing contacts at high temperatures, to activate dopants, results in diffusion of the Si dopants away from the contacts. The result is increased high-frequency (HF) charge trapping and gate leakage current.10 Secondly, increasing the Al concentration in the barrier and/or using AlN exclusion layer is known to increase 2-Dimensional Electron Gas (2DEG) confinement and to enhance 2DEG density and mobility, which enhances performance. 8,9 However, it results in increased R C due to low metal diffusion beneath the metal contact. 11,12 In this work, we propose a fabrication process of ohmic contacts to reduce R C of AlGaN/GaN HEMTs with a high Al concentration, while avoiding implantations that cause HF-traps and gate leakage. This is essential for enhancing device DC and RF performance. For this new proposal, the outer edges of an AlGaN/GaN HEMT, where the source and drain ohmic contacts are to be placed, are etched from the surface of the device down into the AlGaN barrier layer. Contact metal is then evaporated onto the etched locations and rapidly annealed under high temperatures. During the annealing process, contact metal diffuses into the AlGaN barrier layer to form an alloy beneath the metal contact. The change in R C at different etching depths at various annealing conditions is investigated to identify the optimal etching depth given by the lowest R C .The epi-structure of the investigated devices is presented in Device structure section of this paper. The source and drain contact metallization multilayer scheme and ohmic contact formatio...

Low contact resistance and high breakdown voltage of AlGaN/GaN HEMT grown on silicon using both AlN/GaN superlattice and Al0.07Ga0.93N back barrier layer

“…These results suggest that the structure grown in this study represents a substantial enhancement in contact resistance for AlGaN/GaN heterostructures as compared to the device reported in [26][27][28]. It also reaches the value for the ohmic recess technique in [29,30], therefore demonstrating high-quality AlGaN/GaN HEMT heterostructures on silicon. The lateral leakage current and breakdown voltage of the heterostructures grown on Si with and without BB were evaluated using a TLM structure with a spacing of 10 µm, as shown in figure 6(a).…”

Optimization of Contact Resistance and DC Characteristics for AlGaN/GaN HEMTs Utilizing Sub-10 nm Nanohole Etching

“…The contact resistance measurement was determined using TLM patterns with spacings (𝑑) of 12, 14, 18, and 26 μm, and the width (𝑊) was 100 μm. Measurements of total resistance (𝑅 𝑇 ) across each contact pair were measured to construct the TLM graph [34] using a four-point probe arrangement, as shown in Figure 4. The measured 𝑅 𝑇 can be expressed by Equation (1) as follows:…”

“…To date, the exploration of etching patterns to minimize ohmic contact resistance has pursued several directions, including the analysis of various pattern morphologies and arrangements [19,[23][24][25], pattern dimensions [22,24,25,32], and etching depths [22][23][24]. Among the diverse etching pattern morphologies paired with different arrangements, commonly utilized ones are symmetrically arranged holes [19,[22][23][24]32,34], closely packed holes [38], and lines in the direction of current flow [19,25]. Additionally, some groups have crafted grid-like patterns composed of horizontal and vertical lines [23] and patterns where the holes gradually increase in size from small to large [24], in which You et al investigated the effects of various hole array arrangements on ohmic contact, confirming that devices with gradually increasing hole patterns of 1/3/5 μm demonstrated lower contact resistance compared to those with uniformly sized patterns.…”

“…The results showed that the optimized annealing temperature for AlGaN/GaN heterostructures with etched hole arrays was 40 °C lower than that for conventional structures [38]. Additionally, to address the issue of current collapse, some groups have used an Au-free Ti/Al/Ti for ohmic contacts with a low annealing temperature of 550 °C, creating Al-GaN/GaN HEMTs with a low thermal budget and reduced contact resistance [33,34]. In this work, we used an 850 °C annealing temperature for the ohmic metal for 30 s. Given that the annealing temperature can significantly impact contact resistance increased from 0.2 to around 0.35 Ω-mm when the annealing temperature increased from 800 to 820 °C, further optimization of the annealing temperature and annealing time for nanoscale patterned ohmic contacts is necessary to allow the ohmic metal to effectively infiltrate the etched holes in AlGaN and achieve better TiN phase formation.…”

AlGaN/GaN High-Electron-Mobility Transistors on a Silicon Substrate Under Uniaxial Tensile Strain

“…3,4 In recent years, the application of GaN to silicon substrate has become increasingly widespread due to its low cost, larger size, acceptable thermal conductivity, and ease of integration with complementary-metal-oxide semiconductor circuits. 5,6 The challenges of GaN-on-silicon high-electron-mobility transistors (HEMTs) include lossy substrates and large thermal expansion coefficient mismatches between GaN and Si substrates. 7 Several studies have reported the backgrind and backside metallization of HEMT on silicon substrate for compact packages and efficient heat dissipation.…”