Low Subthreshold Slope AlGaN/GaN MOS-HEMT with Spike-Annealed HfO2 Gate Dielectric

Yeom, Min Jae; Yang, Jeong Yong; Lee, Chan Ho; Heo, Junseok; Chung, Roy B.; Yoo, Geonwook

doi:10.3390/mi12121441

Cited by 7 publications

(4 citation statements)

References 27 publications

(34 reference statements)

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“…In Figure e, we calculate the subthreshold slope (SS), defined as the change in gate voltage necessary to change the drain current by one decade. The SS should be minimized to reduce the switching power loss . We find SS values of 542 ± 62, 339 ± 64 and 182 ± 36 mV/dec for the MoS 2 (yellow), WS 2 (green), and WSe 2 (orange) transistors, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…The SS should be minimized to reduce the switching power loss. 49 We find SS values of 542 ± 62, 339 ± 64 and 182 ± 36 mV/dec for the MoS 2 (yellow), WS 2 (green), and WSe 2 (orange) transistors, respectively. Since SS ∝ 1/ C device , 50 our SS is expected to be low (<600 mV/dec) since we use a high C device ≈ 3.1 μF cm −2 , attributed to the ionic liquid EMIM TFSI.…”

Section: Resultsmentioning

confidence: 99%

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High-Mobility Flexible Transistors with Low-Temperature Solution-Processed Tungsten Dichalcogenides

et al. 2023

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The investigation of high-mobility two-dimensional (2D) flakes beyond molybdenum disulfide (MoS 2 ) will be necessary to create a library of high-mobility solution-processed networks that conform to substrates and remain functional over thousands of bending cycles. Here we report electrochemical exfoliation of large-aspect-ratio (>100) semiconducting flakes of tungsten diselenide (WSe 2 ) and tungsten disulfide (WS 2 ) as well as MoS 2 as a comparison. We use Langmuir− Schaefer coating to achieve highly aligned and conformal flake networks, with minimal mesoporosity (∼2−5%), at low processing temperatures (120 °C) and without acid treatments. This allows us to fabricate electrochemical transistors in ambient air, achieving average mobilities of μ MoSd 2 ≈ 11 cm 2 V −1 s −1 , μ WSd 2 ≈ 9 cm 2 V −1 s −1 , and μ WSed 2 ≈ 2 cm 2 V −1 s −1 with a current on/off ratios of I on /I off ≈ 2.6 × 10 3 , 3.4 × 10 3 , and 4.2 × 10 4 for MoS 2 , WS 2 , and WSe 2 , respectively. Moreover, our transistors display threshold voltages near ∼0.4 V with subthreshold slopes as low as 182 mV/dec, which are essential factors in maintaining power efficiency and represent a 1 order of magnitude improvement in the state of the art. Furthermore, the performance of our WSe 2 transistors is maintained on polyethylene terephthalate (PET) even after 1000 bending cycles at 1% strain.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

High-Mobility Flexible Transistors with Low-Temperature Solution-Processed Tungsten Dichalcogenides

et al. 2023

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“…By utilizing the following equation, the interface trap density ( D it ) can be estimated from the SS value: where k is Boltzmann constant, T is temperature and C STO is the capacitance of STO 23 , 24 . The estimated D it at room temperature is approximately 6.33 × 10 11 eV −1 cm −2 , which is even lower than MOS-HEMTs with conventional amorphous-based gate dielectric materials 13 , 35 . Thus, the steep SS of our device, which originates from the clean interface of the STO/GaN HEMT, indicates excellent gate controllability, and shows that it’s an advantageous structure for low power consumption applications.…”

Section: Resultsmentioning

confidence: 82%

Heterogeneous integration of high-k complex-oxide gate dielectrics on wide band-gap high-electron-mobility transistors

Ji,

Yang,

Lee

et al. 2024

Commun Eng

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Heterogeneous integration of dissimilar crystalline materials has recently attracted considerable attention due to its potential for high-performance multifunctional electronic and photonic devices. The conventional method for fabricating heterostructures is by heteroepitaxy, in which epitaxy is performed on crystallographically different materials. However, epitaxial limitations in monolithic growth of dissimilar materials prevent implementation of high quality heterostructures, such as complex-oxides on conventional semiconductor platforms (Si, III-V and III-N). In this work, we demonstrate gallium nitride (GaN) high-electron-mobility transistors with crystalline complex-oxide material enabled by heterogeneous integration through epitaxial lift-off and direct stacking. We successfully integrate high-κ complex-oxide SrTiO3 in freestanding membrane form with GaN heterostructure via a simple transfer process as the gate oxide. The fabricated device shows steep subthreshold swing close to the Boltzmann limit, along with negligible hysteresis and low dynamic on-resistance, indicating very low defect density between the SrTiO3 gate oxide and GaN heterostructure. Our results show that heterogeneous integration through direct material stacking is a promising route towards fabricating functional heterostructures not possible by conventional epitaxy.

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“…It is worth mentioning that the H-radical treatment and ALD deposition were performed on a cluster platform with no vacuum break. Post-dielectric annealing was carried out in an N 2 ambient at 550 °C for 40 s [ 27 , 28 ]. Then, mesa-isolation was performed by Inductive Coupled Plasma (ICP) etching.…”

Section: Device Characterizationmentioning

confidence: 99%

In Situ H-Radical Surface Treatment on Aluminum Gallium Nitride for High-Performance Aluminum Gallium Nitride/Gallium Nitride MIS-HEMTs Fabrication

Yang,

Fan,

Zhang

et al. 2023

Micromachines

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In this work, we demonstrated a low current collapse normally on Al2O3/AlGaN/GaN MIS-HEMT with in situ H-radical surface treatment on AlGaN. The in situ atomic pretreatment was performed in a specially designed chamber prior to the thermal ALD-Al2O3 deposition, which improved the Al2O3/AlGaN interface with Dit of ~2 × 1012 cm−2 eV−1, and thus effectively reduced the current collapse and the dynamic Ron degradation. The devices showed good electrical performance with low Vth hysteresis and peak trans-conductance of 107 mS/mm. Additionally, when the devices operated under 25 °C pulse-mode stress measurement with VDS,Q = 40 V (period of 1 ms, pulse width of 1 μs), the dynamic Ron increase of ~14.1% was achieved.

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Low Subthreshold Slope AlGaN/GaN MOS-HEMT with Spike-Annealed HfO2 Gate Dielectric

Cited by 7 publications

References 27 publications

High-Mobility Flexible Transistors with Low-Temperature Solution-Processed Tungsten Dichalcogenides

High-Mobility Flexible Transistors with Low-Temperature Solution-Processed Tungsten Dichalcogenides

Heterogeneous integration of high-k complex-oxide gate dielectrics on wide band-gap high-electron-mobility transistors

In Situ H-Radical Surface Treatment on Aluminum Gallium Nitride for High-Performance Aluminum Gallium Nitride/Gallium Nitride MIS-HEMTs Fabrication

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