Low-Supply Sensitivity <i>LC</i> VCOs With Complementary Varactors

Gui, Xiaoyan; Tang, Bingjun; Tang, Ruihua; Li, Dan; Geng, Li

doi:10.1109/tvlsi.2020.2991765

Cited by 12 publications

(10 citation statements)

References 25 publications

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“…By measuring the power levels of outputs at center frequency and supply-noise induced side tones through the signal analyzer, the supply sensitivity was evaluated [9]. Fig.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…The overall performance of the proposed M-PSR LO generator is compared with state-of-the-art supplyinsensitive designs as shown in Table I. Supply sensitivity can be further deduced based on P0/P1 and intuitively FOMss [9] and FOMa [15] are defined as: It takes into consideration of the FOM for normalized supply sensitivity and for area respectively together with the standard FOM for phase noise, working frequency and power consumption [9]. The proposed LO generator achieves a competitive FOMss and FOMa among state-of-the-art works.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…Nevertheless, it is only applicable in the structure with a tail current source. The compensation [9] and cancellation [10] techniques based on characteristics of devices can reject supply noise, which is applicable for circuits with or without the tail current source. However, the power supply rejection capability is achieved in open loop which will introduce additional noise to output directly.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique

Zhou¹,

Ding

Boon

et al. 2021

IEEE Access

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This paper presents a supply-insensitive low-power quadrature local oscillation (LO) generator based on the current-reused voltage-controlled oscillator (VCO) and divide-by-two frequency divider (FD). By utilizing the mutual power-supply rejection (M-PSR) technique, a voltage regulator is embedded into the FD to provide a supply-insensitive voltage for VCO. Meanwhile, the feedback loop provides a supply-insensitive current and time constant compensation for FD. The M-PSR technique does not require extra voltage headroom, thus the proposed quadrature LO generator can work under the supply of 0.9 V. A prototype of the proposed quadrature LO generator is implemented in a 28-nm CMOS process. Measurement results indicate that the LO generator achieves a phase noise of -110.5 dBc/Hz@1MHz at the carrier of 5.9 GHz and the power consumption is 1.8 mW. This work has a competitive figure of merit in supply sensitivity or in area (FOMss or FOMa respectively) among the state-of-the-art works.

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“…By measuring the power levels of outputs at center frequency and supply-noise induced side tones through the signal analyzer, the supply sensitivity was evaluated [9]. Fig.…”

Section: Measurement Resultsmentioning

confidence: 99%

Section: Measurement Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique

Zhou¹,

Ding

Boon

et al. 2021

IEEE Access

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“…It could be argued that the most recent researches in LC oscillators are derived from an innovative change in differential Colpitts and cross-coupled oscillators. [11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28] A precise study of PN in these oscillators was conducted in Andreani et al 29 and according to Hajimiri's method. The results show that the cross-coupled oscillator has better PN than the other one.…”

Section: Standardmentioning

confidence: 99%

Phase noise suppression in LC oscillators: Tutorial

Bagheri

2021

Circuit Theory & Apps

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This paper presents a comprehensive study of phase noise (PN) suppression in LC-tank oscillators. The goal of this study is to provide designers with the latest techniques for reducing PN in cross-coupled oscillators. To this end, we begin with a discussion of two prevalent PN models in oscillators: Hajimiri and Demir. We prefer the Hajimiri model because it does not involve very complicated math, and it offers engineers better insight into designing low-PN oscillators in the two-PN close-in regions in an oscillator spectrum (1/f 2 and 1/f 3 ). In 1/f 2 region, we show that a need for a large output-voltage swing leads to Class D and B oscillators, and a large output-current swing results in Class C oscillators. Also, reduction of the impulse sensitivity functions (ISFs) of an oscillator core can happen in Class F oscillators. A few solutions are presented for mitigating flicker noise up-conversion, such as adding resistances, controlling the oscillation amplitude, decreasing the conduction angle, guiding the high-frequency harmonics of current, and shifting the phase of V GS against V DS . We also provide a comparison of recent state-of-the-art literature to show what constitutes a good PN in both 1/f 2 and 1/f 3 regions in cross-coupled oscillators. We conclude that a cross-coupled oscillator can reach the best performances in 1/f 3 and 1/f 2 PN regions if the oscillator is designed in Class C with the K block and uses the techniques of narrowing the conduction angle, the tail inductor, and the modified tank simultaneously.

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“…First, since the switched-capacitor-based dc-dc converters are generally clocked at several or tens of MHz, the induced variation on oscillator frequency could hardly be suppressed by PLLs with a typical bandwidth of <1 MHz. 1 Hence, several techniques have been proposed in the literature to reduce the supply pushing of the oscillator [5]- [15]. However, most of these techniques are only effective for tiny (e.g., 1 mV) [5] or low frequency (<1 MHz) [6], [7], [10], [13] supply ripples or would require high power and area overhead [11], [12].…”

Section: Introductionmentioning

confidence: 99%

A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple

Chen

Gong

Staszewski

et al. 2022

IEEE J. Solid-State Circuits

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In this article, we present a 4.5-5.1-GHz fractional-N digitally intensive phase-locked loop (DPLL) capable of maintaining its performance in face of a large supply ripple, thus enabling a direct connection to a switched-mode dc-dc converter. Supply pushing of its inductor-capacitor (LC) oscillator is suppressed by properly replicating the supply ripple onto the gate of its tail current transistor, while the optimum replication gain is determined by a new on-chip calibration loop tolerant of supply variations. A proposed configuration of cascading a supply-insensitive slope generator with an output of a current digital-to-analog converter (DAC) linearly converts the phase error timing into a corresponding voltage, which is then quantized by a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a digital phase error. We also introduce a low-power ripple pattern estimation and cancellation algorithm to remove the phase error component due to the supply-induced delay variations of loop components. Implemented in 40-nm CMOS, the DPLL prototype achieves the performance of 428-fs rms jitter, <−55-dBc fractional spur, and <−54-dBc maximum spur while consuming 3.25 mW and being subjugated to a sinusoidal or sawtooth supply ripple of 50 mV pp at 50-MHz reference divided by 3, 6, or 12.

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Low-Supply Sensitivity LC VCOs With Complementary Varactors

Cited by 12 publications

References 25 publications

A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique

A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique

Phase noise suppression in LC oscillators: Tutorial

A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <−54-dBc Spurs Under 50-mVpp Supply Ripple

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