Low temperature backside damascene processing on temporary carrier wafer targeting 7μm and 5μm pitch microbumps for N equal and greater than 2 die to wafer TCB stacking

Derakhshandeh, Jaber; Beyne, Eric; Beyer, Gerald; Capuz, Giovanni; Cherman, Vladimir; Preter, Inge De; Gerets, Carine; Shafahian, Ehsan; Kennes, Koen; Jamieson, Geraldine; Cochet, Tom; Webers, Tomas; Tobback, Bert; Plas, G. Van der; Tulipe, D.C. La; Phommahaxay, Alain; Miller, Andy

doi:10.1109/ectc51906.2022.00179

Cited by 8 publications

(2 citation statements)

References 5 publications

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“…The alignment accuracies in XY directions are found to be ±10 μm, and the maximum angular alignment error is 7°. The XY positional accuracies ±10 μm are acceptable even with the worst angular error, considering that, for example, highly reliable results have been obtained for fine-pitch microbump interconnections with an inter-bump space of 5 μm [13]. The alignment errors would slightly increase DC resistance to drive the µLEDs through the Cu pillars.…”

Section: Resultsmentioning

confidence: 91%

Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED

Susumago

Liu

Hoshi

et al. 2023

IEEE Electron Device Lett.

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This letter describes a direct Cu bonding technology to there-dimensionally integrate heterogeneous dielets based on a chip-on-wafer configuration. 100-μm-cubed blue μLEDs temporarily adhered on a photosensitive resin are interconnected by semi-additive plating (SAP) without thermal compression bonding. By using SAP bonding, a lot of dielets can be stacked on thin 3D-IC chiplets. The following three key technologies are applied to solve the yield issues of SAP bonding. After pick-and-place assembly, additional coplanarity enhancement eliminates Cu bridges grown to a small gap between the μLEDs and photosensitive resin. The μLEDs arrays with sidewalls insulated by room-temperature ozone-ethylene-radical (OER)-SiO2-CVD are successfully bonded on sapphire wafers and a thin 3D-IC with through-Si via (TSV). Further design optimization is required, but partial seed pre-etching works well to increase the yield. Fully integrated module implementation with the 3D-ICs will be the next stage, however, we discuss a superior prospect for yield enhancement toward nearly 100%.

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Section: Resultsmentioning

confidence: 91%

Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED

Susumago

Liu

Hoshi

et al. 2023

IEEE Electron Device Lett.

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show abstract

“…This approach will avoid a shockwave generation and enable a release step fully integrated in the die bonder, without the need of a difficult and expensive integration of an excimer laser. This UV release layer should however be capable to withstand all wafer and die preparation processes, including die singulation, cleaning and activation, and potentially even dielectric deposition [21] and damascene processing [22]. Alternatives such as thermal release materials are less attractive since they are not compatible with higher temperatures during wafer/die preparation steps.…”

Section: Ultra-thin Die Pick and Placementioning

confidence: 99%

Optimized Die Preparation and Handling for High Yield Hybrid Die to Wafer Bonding

Bex,

Phommahaxay,

Kennes

et al. 2024

IMAPSource Proceedings

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Hybrid Cu/dielectric bonding is a well-established technology for Wafer-To-Wafer (W2W) bonding, but it is challenging to apply this technology to Die-To-Wafer (D2W) bonding. Very small particles on the die or wafer can lead to voids/non-bonded regions. Processes to clean and activate wafers for hybrid W2W are quite mature, but it is very challenging to apply these to thinned and singulated dies for D2W bonding. To allow a (partial) re-use of the existing wafer level cleaning, metrology and activation processes and equipment, we propose a new concept where dies are being singulated, cleaned and activated on a glass carrier wafer. After the die preparation steps, the dies are directly picked from the carrier wafer. This approach does not involve additional pick & place steps and avoids the use of conventional dicing tapes. The first direct dielectric D2W bonding experiments using this new approach show a very promising bonding yield, with a high number of completely void-free bonded 50 μm thin dies. Additionally, by eliminating dicing tapes, thinned wafers and singulated dies are always supported by a rigid surface, enabling ultrathin die handling. In this study we also report the handling of dies down 10 μm thickness.

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Effect of Co-W and Co-Fe-W Diffusion Barriers on the Reliability of the Solder/Cu Interface during Reflow Conditions

Liu,

Li,

Chen

et al. 2024

Electron. Mater. Lett.

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Low temperature backside damascene processing on temporary carrier wafer targeting 7μm and 5μm pitch microbumps for N equal and greater than 2 die to wafer TCB stacking

Cited by 8 publications

References 5 publications

Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED

Room-Temperature Direct Cu Semi-Additive Plating (SAP) Bonding for Chip-on-Wafer 3D Heterogenous Integration With μLED

Optimized Die Preparation and Handling for High Yield Hybrid Die to Wafer Bonding

Effect of Co-W and Co-Fe-W Diffusion Barriers on the Reliability of the Solder/Cu Interface during Reflow Conditions

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