Low-Temperature Solution-Processed HfZrO Gate Insulator for High-Performance of Flexible LaZnO Thin-Film Transistor

Abstract

Metal-oxide-semiconductor (MOS)-based thin-film transistors (TFTs) are gaining significant attention in the field of flexible electronics due to their desirable electrical properties, such as high field-effect mobility (μFE), lower IOFF, and excellent stability under bias stress. TFTs have widespread applications, such as printed electronics, flexible displays, smart cards, image sensors, virtual reality (VR) and augmented reality (AR), and the Internet of Things (IoT) devices. In this study, we approach using a low-temperature solution-processed hafnium zirconium oxide (HfZrOx) gate insulator (GI) to improve the performance of lanthanum zinc oxide (LaZnO) TFTs. For the optimization of HfZrO GI, HfZrO films were annealed at 200, 250, and 300 °C. The optimized HfZrO-250 °C GI-based LaZnO TFT shows the μFE of 19.06 cm2V−1s−1, threshold voltage (VTH) of 1.98 V, hysteresis voltage (VH) of 0 V, subthreshold swing (SS) of 256 mV/dec, and ION/IOFF of ~108. The flexible LaZnO TFT with HfZrO-250 °C GI exhibits negligible ΔVTH of 0.25 V under positive-bias-temperature stress (PBTS). The flexible hysteresis-free LaZnO TFTs with HfZrO-250 °C can be widely used for flexible electronics. These enhancements were attributed to the smooth surface morphology and reduced defect density achieved with the HfZrO gate insulator. Therefore, the HfZrO/LaZnO approach holds great promise for next-generation MOS TFTs for flexible electronics.

Advancements in Metal Oxide Thin Film Quality in Solution-Processed High-κ Dielectrics for High-Performance Transistors

“…This is due to its smooth surface, enhanced M−O−M network, and lower defect states at the interface between the gate dielectric and the semiconductor layer. 30,31,33,40 Optimization of Dielectric Properties through Modifications in Processing. A high-quality dielectric layer in a TFT restricts the current flow, facilitating electrical conduction solely through the interface between semiconductor and dielectric layers.…”

“…UV−O 3 -treated ZrO x and Hf-, La-, and Al-doped ZrO x gate insulators exhibit a smaller V TH shift under bias stress compared to pristine ZrO x . 31,33 Notably, the subthreshold swing SS remains unchanged even after 1 h bias stress, indicating the absence of traps (i.e., interfacial traps) at the interface between the gate insulator and the channel layer. This is attributed to the lower trap density at the gate dielectric and active layer interface.…”

“…Both Hf (Hf−O, binding energy: 801 kJ/mol) and La (La−O, binding energy: 799 kJ/mol) form strong bonds with oxygen (O), contributing to a robust M−O−M network and ensuring a high-quality interface between the gate insulator and the channel layer. 31,33 Under UV irradiation, metal oxide films undergo the decomposition of oxygen molecules into oxygen radicals (•O), forming ozone (O 3 ) (Figure 7a We have included the recent studies on metal oxide-based TFT with solution-processed gate insulators in this manuscript. Several studies have demonstrated promising results for highperformance metal-oxide TFTs utilizing solution-processed gate insulators such as HfO 2 , AlO x , ZrO x , and their doped variations.…”

“…Several challenges are associated with such deposition, including concerns related to uniformity, surface roughness, control over film thickness, scattered mass density, defect traps, and issues related to adhesion. − These challenges can be addressed by employing various modifications on the dielectric layer to further enhance the properties such as high mobility, lower threshold voltage, negligible hysteresis, and electrical stability of TFTs. Various techniques are employed to address these challenges, including the use of purified precursor, alloying or doping with different cations, UV–ozone treatment, and Ar–O 2 plasma treatment, to name a few. − …”

“…The absence of hysteresis voltage, low leakage current, reduced subthreshold swing (SS), and high ON-current can be attributed to the minimal trap density at the interface between the gate dielectric and the channel semiconductor. ,, The AFM analysis (Figure ) and XPS data (Figure ) confirm that the optimal doping ratio of Hf, Al, and La in ZrO x gate dielectric renders it a favorable candidate. This is due to its smooth surface, enhanced M–O–M network, and lower defect states at the interface between the gate dielectric and the semiconductor layer. ,,, …”