Low temperature touch down and suppressing filler trapping bonding process with a wafer level pre-applied underfilling film adhesive

Nonaka, Takamasa; Niizeki, Shoichi; Asahi, Noboru; Fujimaru, Koichi

doi:10.1109/ectc.2012.6248869

Cited by 12 publications

(5 citation statements)

References 9 publications

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“…The temperature was increased at 20°C/min. In industry, two type of wafer-level underfill (WLUF) materials have been used: B-stage-type materials [2][3][4] and film-type materials [5][6][7]. The B-stage materials contain low volatility solvents, are liquid at room temperature, and are usually spin coated onto a wafer and heat treated to make B-stage tack-free resin for the wafer dicing process.…”

Section: Thermal Underfill Materials Formulation and Propertiesmentioning

confidence: 99%

Thermally enhanced pre-applied underfills for 3D integration

Horibe

Okamoto

Mori

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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One of the biggest challenges for future high-performance three dimensional (3D) integrated devices is heat removal from the stacked dies. In this study, thermally enhanced preapplied type underfills were studied. These materials were formulated considering fillet cracks and delaminations that appeared in thermal cycling tests on 2D organic package. Finally, the applicability for 3D integration processing with the new material was evaluated on a 3D test vehicle assembly. IntroductionThree-dimensional (3D) chip integration with throughsilicon-vias (TSVs) supports higher performance, lower power, and smaller footprints. Highly integrated 3D devices create higher heat densities due to their small sizes. One of the biggest challenges for future 3D devices is to accelerate the heat transfer within chip stacks. To cool the stack, improving the thermal conductivity of the underfills between the dies is one of the more promising approaches. However, since standard silica-filler-base capillary type underfills do not have good thermal properties due to the low thermal conductivity of the silica filler, some other highly thermally conductive filler must to be selected for these thermally enhanced underfills. Such high-filler-loaded underfills with high thermal conductivity have high viscosities. Therefore, the industry-standard capillary method to add underfills after the chip-join step will not work well for proposed 3D devices with narrow gaps, large dies, or multi-stacked dies. In this study, pre-applied type thermal conductive underfills were studied. The materials with flux chemicals can be applied to wafer, die, or substrate, and then bond the chips and substrates with solder joints. With this type of underfill, not only the reliability but also the processing windows for good solderjoint yield and process capability strongly depend on the material properties. Therefore, some trial and error is necessary in the development. Thermal modeling is used to understand the heat flows and the efficacy of various thermal underfill materials for the 3D stacks [1]. As shown in Fig. 1, a joint layer consisting of solder bumps and a standard underfill (0.4 W/mK) will increase the thermal resistance within a package structure. In this model, if a thermally conductive underfill (2.0 W/mK) is used, then the thermal resistance will be dramatically reduced. At the same time, such thermally enhanced underfills must contain highly thermally conductive fillers. However, since the material properties of such fillers differ from those of standard silica fillers, the formulation of the thermal underfill must be carefully optimized by considering all of the material properties of the compound. It is a major challenge to discover the optimal properties of a

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Section: Thermal Underfill Materials Formulation and Propertiesmentioning

confidence: 99%

Thermally enhanced pre-applied underfills for 3D integration

Horibe

Okamoto

Mori

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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“…TCB (thermal compression bonding) combined with pre applied encapsulation material has also been used for flip chip assembly from the advantage of finer bump pitch capability and stress relief at the bump root. There are two types of pre applied encapsulation material, one is a paste material which is called NCP (Non Conductive Paste) [1] and the other one is NCF (Non Conductive Film) which is a b-stage film [2][3][4]. NCF is a film type adhesive and the character has an advantage of wafer level process compatibility.…”

Section: Introductionmentioning

confidence: 99%

Flip chip assembly with wafer level NCF

Kobayashi

Nonaka

2014

2014 International Conference on Electronics Packaging (ICEP)

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Flip chip assembly with the newly developed pre applied NCF on wafer was demonstrated. The two types of the test vehicle of 7.3 × 7.3 mm 2 and 12.0 × 12.0 mm 2 were used and the NCF was pre laminated on the die side. The NCF applied dies were bonded to the substrate. The dies had Cu pillar bumps with Sn-Ag solder caps in both of the core and the peripheral area. The substrates had Cu/OSP electrode pad. The bonding was carried out at 240 o C. The observations with C-SAM and microscopy which was done after parallel lapping didn't show any void inside the NCF. The microscopic observation at the cross section of the joint of the die bump and the Cu trace on the substrate revealed the formation of good solder welding. The embedded daisy chain circuit resistance measurement indicated achievement of the bump interconnection of both test vehicles of 7.3 × 7.3 mm 2 and 12.0 × 12.0 mm 2 die. Test of the thermal cycle between -55 o C and 125 o C didn't affect either the daisy chain circuit resistance or NCF adhesion.

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“…Especially, to develop effective underfill methods for 3D is unavoidable to relieve mechanical stresses so that the reliabilities of interconnections can be enhanced [7][8][9][10]. However, 3D structure with a thin logic device as a bottom die and Wide I/O DRAM as a top die has a lot of challenges in its assembly process such as: (1) To achieve void less underfill formation under the thin logic die, (2) To prevent underfill resin creeping on the back side of the thin logic die not to affect the memory die stacking, (3) To fill space with the underfill resin under overhangs of the memory die when the memory die is larger than the logic die.…”

Section: Introductionmentioning

confidence: 99%

High density and reliable packaging technology with Non Conductive Film for 3D/TSV

Ono

Watanabe

Ishikawa

et al. 2013

2013 IEEE International 3D Systems Integration Conference (3DIC)

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The innovative flip chip assembly process with Non Conductive Film (NCF) contributes to high density and reliable 3D/TSV integrations has been developed and demonstrated. The target package had two tier structure which consisted of a logic device and Wide I/O DRAM. The logic device was fabricated by via-middle process and accompanied with 1200 TSVs, a thickness of 50 μm and 40 μm / 50 μm bump pitch layout. Thermalcompression bonding method with Cu pillar was applied to both connections between the memory die and the logic die and between the logic die and an organic substrate so that the high reliability could be achieved. In this work, NCF laminated on substrates was selected as an underfill material to establish robust process for 3D integrations and to realize the cost effective assembly. As reliability test items, 1500-cycle temperature cycling test, 1000h high temperature storage test, 1000h high humidity test, 500h unbiased highly accelerated stress test and 300h pressure cooker test were performed. Furthermore, 28 nm logic device and Wide I/O DRAM were assembled into the 3D structure with this new technology and 12.8 GB/s transmission and 89 % reduction of I/O power compared to LPDDR3 were demonstrated.

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Low temperature touch down and suppressing filler trapping bonding process with a wafer level pre-applied underfilling film adhesive

Cited by 12 publications

References 9 publications

Thermally enhanced pre-applied underfills for 3D integration

Thermally enhanced pre-applied underfills for 3D integration

Flip chip assembly with wafer level NCF

High density and reliable packaging technology with Non Conductive Film for 3D/TSV

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