2007
DOI: 10.1116/1.2426976
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Low temperature ZEP-520A development process for enhanced critical dimension realization in reactive ion etch etched polysilicon

Abstract: The authors report on the realization of an enhanced process protocol for producing sub-20nm wide lines with extremely narrow pitches in electron beam resist using a low temperature development process. Linewidths ranging from 10to50nm with a pitch range of 40–250nm have been fabricated on 8in. silicon wafers, using a JEOL JBX 6000 FS/E electron beam lithography tool at 50kV accelerating voltage. ZEP-520A (Nippon Zeon) resist, a nonchemically amplified positive electron beam resist was employed for this effort… Show more

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Cited by 17 publications
(9 citation statements)
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“…One source of sidewall roughness is the line edge roughness in the lithography. Previous works have observed that the temperature of the development step for E-beam resists strongly affects the line edge roughness of E-beam patterns, as observed under SEM [70], [71].…”
Section: A Developmentmentioning
confidence: 87%
“…One source of sidewall roughness is the line edge roughness in the lithography. Previous works have observed that the temperature of the development step for E-beam resists strongly affects the line edge roughness of E-beam patterns, as observed under SEM [70], [71].…”
Section: A Developmentmentioning
confidence: 87%
“…This is in agreement with previous studies on cold development of Poly͑methyl methacrylate͒ ͑PMMA͒ 15-17 and ZEP 520. 15,18 …”
Section: Introductionmentioning
confidence: 98%
“…EBL can pattern arbitrary features with a resolution of approximately 10 nm. [2,3] Silicon stamps were then treated with fluorinated silane prior to the metal deposition. The presence of a fluorinated silane interface between the relief pillar and the metallic film weakens the adhesion between the latter two and facilitates the transfer of metallic disks.…”
Section: Results and Discussion Ntp Process Descriptionmentioning
confidence: 99%