Low-Transition Test Pattern Generation for BIST-Based Applications

Nourani, Mehrdad; Tehranipoor, Mohammad; Ahmed, Nisar

doi:10.1109/tc.2007.70794

Cited by 61 publications

(84 citation statements)

References 27 publications

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“…The GLFSR (Pradhan and Gupta, 1991) structure is modified into it automatically inserts three intermediate patterns between its original pairs genearated. The intermediate patterns are carefully chosen using bipartite and bit insertion techniques (Nourani et al, 2008) and impose minimal time to achieve desired fault coverage. Insertion of Intermediate pattern is achieved based on non overlapping clock scheme (Girard et al, 2001).…”

Section: Proposed Workmentioning

confidence: 99%

“…EGLFSR is an enhanced GLFSR, using more XOR gate in a test pattern generator which achieves a better performance. Nourani et al (2008) It has more transition in between each bits of the pattern generated and (Sakthivel and Kumar, 2011) an adjacent bits of test patterns generated by LT-GLFSR is swapped by using multiplexer is called as bit swapping low transition generalized linear feedback shift register.In this method, generated patterns has greater degree of randomness and high corelation between consecutive patterns but it has slightly high transitions in sequence of patterns generated. Generally, power consumption is with respect to number of transition between cosecutive patterns, if transition is more, power consumption is more in test pattern generator and CUT.…”

Section: Introductionmentioning

confidence: 99%

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Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

Mohamed¹

2012

American Journal of Applied Sciences

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Problem statement:In Built-In Self-Test (BIST), test patterns are generated and applied to the Circuit-Under-Test (CUT) by on-chip hardware; minimizing hardware overhead is a major concern of BIST implementation. In pseudorandom BIST architectures, the test patterns are generated in random nature by linear feedback shift registers. This normally requires more number of test patterns for testing the architectures which need long test time. Approach: This study presents a novel test pattern generation technique called Low-Transition Generalized Linear Feedback Shift Register (LT-GLFSR) with bipartite (half fixed) and bit insertion (either 0 or 1) techniques. Intermediate patterns (by bipartite and bit (either 0 or 1) insertion technique) inserted in between consecutive test patterns generated by GLFSR which is enabled by a non overlapping clock scheme. This process is performed by finite state machine generate sequence of control signals. Low-Transition Generalized Linear Feedback Shift Registers (LT-GLFSR), are used in a circuit under test to reduce the average and peak power during transitions. LT-GLFSR patterns high degree of randomness and correlation between consecutive patterns. LT-GLFSR does not depend on circuit under test and hence it is used for both BIST and scan-based BIST architectures. Results and Conclusion: Simulation results prove that this technique has reduction in power consumption and high fault coverage with minimum number of test patterns. The results also show that it reduces the peak and average power consumption during test for ISCAS'89 bench mark circuits.

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Section: Proposed Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

Mohamed¹

2012

American Journal of Applied Sciences

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“…This can cause excessive power dissipation. Studies show that the extra average or peak power consumption can create such problem as instantaneous power surge [1]. That may cause circuit damage, and reduces product yield and lifetime.…”

Section: Introductionmentioning

confidence: 99%

“…There are many hardware approaches to reduce test power. Examples are LT-LFSR [1], the modified LFSR structure [2], DS-LFSR [3], LT-RTPG [4] and the two-vectorinhibiting TPG [5].…”

Section: Introductionmentioning

confidence: 99%

A unified solution to reduce test power and test volume for Test-per-scan schemes

Lei

Wang

Liu

et al. 2010

IEICE Electron. Express

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This paper proposes a unified solution to reduce test power and test volume for test-per-scan schemes. With the self-testing using MISR and Parallel SRSG (STUMPS) architecture and the developed reconfigurable Johnson counter, the proposed test pattern generator (TPG) applies two transition sequences to all scan chains, and the primary inputs of the circuit under test (CUT) keep unchanged at most times. Therefore, the switching activities both in the combinational block and in scan chains can be reduced simultaneously. If the generated test vectors that do not contribute to fault coverage are filtered out, the remaining deterministic patterns show the favorable features of high compressible and low-test power. Simulation results on ISCAS'89 benchmarks demonstrate that the proposed TPG imposes negligible impact on test length and power overhead of the CUT.

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“…This can cause excessive power dissipation, and may cause circuit damage and difficulty in performance verification. More advanced techniques have been widely studied and applied for testper-scan BIST scheme [2]. However, there are several approaches for testper-clock BIST applications.…”

Section: Introductionmentioning

confidence: 99%

A low cost test pattern generator for test-per-clock BIST scheme

Lei

Wang

Liu

et al. 2010

IEICE Electron. Express

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Abstract:Test power and test overhead are crucial to VLSI and SOC testing. This paper proposes a low cost test pattern generator (TPG) for test-per-clock built-in self-test (BIST) scheme. The proposed method utilizes a two-dimensional TPG and a bit-XOR array to reduce area overhead, and generates single input change (SIC) sequences to reduce input transitions of the circuit under test (CUT). Simulation results on ISCAS benchmarks demonstrate that the proposed method can achieve high fault coverage and effectively reduce test power. Keywords: Built-in self-test, test-per-clock, test pattern generation, single input change, low power Classification: Integrated circuits References[1] R. S. Katti, X. Ruan, and H. Khattri, "Multiple-output low-power linear feedback shift register design," IEEE Trans.

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Low-Transition Test Pattern Generation for BIST-Based Applications

Cited by 61 publications

References 27 publications

Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

Low Transition Test Pattern Generator Architecture for Built-in-Self-Test

A unified solution to reduce test power and test volume for Test-per-scan schemes

A low cost test pattern generator for test-per-clock BIST scheme

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