Low voltage analog circuit design techniques

Rajput, Shyam Singh; Jamuar, Sudhanshu Shekhar

doi:10.1109/mcas.2002.999703

Cited by 221 publications

(89 citation statements)

References 21 publications

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“…Self-cascode [11][12][13][14][15] is the new technique, which does not require high compliance voltages at output nodes. It provides high output impedance to give high output gain and so it is useful in low-voltage design.…”

Section: Self Cascode Techniquementioning

confidence: 99%

Low Power Folded Cascode OTA

Kundra¹

2012

VLSICS

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Section: Self Cascode Techniquementioning

confidence: 99%

Low Power Folded Cascode OTA

Kundra¹

2012

VLSICS

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“…This property of a composite transistor makes its self-cascode structure ideal for use in low voltage applications, substituting the conventional cascode structure, which has a larger saturation voltage [9]. The equivalent saturation voltage of a TST is proportional to the pinch-off voltage, which is the same for MD and MS (proportional only to V G ).…”

Section: Saturation Voltage Analysismentioning

confidence: 99%

Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors

Conrad

Cortes

Bampi

et al. 2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

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The design of analog integrated circuits together with mixedsignal applications in deep sub-micron technologies is a difficult task, since state-of-the-art technologies and minimum channel length transistors, suitable for digital circuits, are very rarely optimized for analog block design. Non-desired effects are presenting in the shortest transistors, leading mainly to a high output conductance, which is disadvantageous for DC voltage gain stages. We present measurement results supporting the associations of transistors concept to be used in such applications: the T-Shaped Transistor (TST) [1]. The main characteristic of this association is its trapezoidal nature, with no limit on the sizes of the unit composite transistors, providing lower output conductance and saturation voltage in comparison to regular configurations. Such electrical characteristics are demonstrated by means of electrical simulations and electrical measurements of a test chip fabricated by MOSIS in an IBM 0.18µm CMOS process.

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“…Of late, the threshold voltage value is not expected to be smaller in future, hence this value appears as an obstacle facing the input signal that causes a limitation of the input voltage range of the analog circuits. As a consequence, several design techniques were proposed to overcome the upper mentioned limitation [2].…”

Section: Introductionmentioning

confidence: 99%

Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

et al. 2017

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In this work, a new realization topology of the low-voltage ultra-low-power quadrature oscillator is presented. This quadrature oscillator utilizes only two active elements, namely differential voltage current conveyor (DVCC), and five passive ones, all of them are grounded, which is recommended for the integrated circuit implementation. The DVCC is based on quasi-floating-gate MOS transistor, which is a distinct technique from the conventional one, featuring with operation at low-voltage and ultra-low-power conditions; hence the proposed DVCC works with low supply voltage of ± 400 mV and consumes power of merely 6.6 µW. Thanks to these features the total power dissipation of the oscillator is only 0.28 mW. The simulation results using 0.18 µm TSMC CMOS technology are included in order to prove the design correctness.

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Low voltage analog circuit design techniques

Cited by 221 publications

References 21 publications

Low Power Folded Cascode OTA

Low Power Folded Cascode OTA

Early voltage and saturation voltage improvement in deep sub-micron technologies using associations of transistors

Quadrature oscillator based on novel low-voltage ultra-low-power quasi-floating-gate DVCC

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