Low-voltage dynamic BiCMOS CLA circuit with carry skip using novel full-swing logic

Hasan, S. M. Rezaul; Rajagopal, C.

doi:10.1109/4.553180

Cited by 4 publications

(7 citation statements)

References 12 publications

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“…Figure 3(a) shows the N-cell of a full-swing dynamic BiCMOS circuit technique with precharge (clock low) and evaluation (clock high) cycles as discussed in Ref. [7] (the H&R structure). Here, at the end of a high-to-low logic evaluation (clock still high), the PMOS Py turns on and the NMOS M6 turns off in a bid to pull-up the gate of the M ETER to VDD (and turn it off).…”

Section: Charge Redistributionmentioning

confidence: 99%

“…[4] provided a closed form design optimization through transistor reordering for minimum expected dynamic power dissipation in the internal nodes of the MOSFET chain of a CMOS NAND gate. In this paper, we have focused on the dynamic BiCMOS logic gates (reported by several authors, [5,7,9]), and, have proposed improved transistor reordered structures based on a deterministic (rather than probabilistic) power dissipation measure. Small reduction in the gate delay-time is also achieved by this transistor reordering.…”

Section: Introductionmentioning

confidence: 99%

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Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

Hasan

Wahab

2002

VLSI Design

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This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

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Section: Charge Redistributionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

Hasan

Wahab

2002

VLSI Design

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“…As a result, the base of Q1 is isolated from the circuit to confine the excess minority charge in the base. Due to the capacitive coupling between gate and drain of MP3 and between output node and base of Q1, the base voltage of Q1 can be bootstrapped up beyond , and thus, the output can be pulled up nearly to [4], [9]. Thus, the fast near-full-swing operation can be performed at a considerably higher speed than by using the feedback technique [3].…”

Section: New Tspc Bicmos Dynamic Logicmentioning

confidence: 99%

“…Recently, many BiCMOS dynamic logic circuits have been proposed [2]- [5]. In the BiCMOS dynamic logic circuits proposed in [2]- [4], the N-P domino circuit structure with alternatively connected N-cell and P-cell [6], [7] is adopted. But the high-speed pipelined operation is not considered.…”

mentioning

confidence: 99%

“…In the proposed new logic circuits, the true-single-phase clocking (TSPC) scheme is used so that the clock driving and distribution are simple and less chip area is occupied by clock lines [10]- [19]. Furthermore, the bootstrapping technique [4], [9], [20], [21] is used to obtain fast operation and nearfull-swing output. It is shown that under 2-V operation, the new BiCMOS dynamic logic circuits and latch logic circuits, as well as the formed new pipelined logic circuits, have better speed performance than both conventional BiCMOS and CMOS design.…”

mentioning

confidence: 99%

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A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications

Tseng

1999

IEEE J. Solid-State Circuits

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New true-single-phase-clocking (TSPC) BiCMOS/ BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1-m BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clockhigh-evaluate-BiCMOS dynamic latch logic circuit and clock-lowevaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1-m BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications. Index Terms-BiCMOS pipelined system, low-voltage BiCMOS dynamic logic circuits, true single-phase clocking (TSPC). I. INTRODUCTION B iCMOS technology has been widely applied to the design of memories and high-performance very-large-scale integrated circuit (VLSI) logic due to its advantageous features of high speed, high driving capability, and low power dissipation [1]. In the design of conventional BiCMOS static logic circuits, extra PMOS devices should be used with NMOS devices to realize logic functions. As a consequence, the chip area is large, especially in complex logic. Also, both power dissipation and speed performance are degraded.

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600MHz BiCMOS digitally controlled oscillator for clock recovery and frequency synthesis PLLs

Hasan¹,

Yusof²,

Aun³

2001

International Journal of Electronics

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Low-voltage dynamic BiCMOS CLA circuit with carry skip using novel full-swing logic

Cited by 4 publications

References 12 publications

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications

600MHz BiCMOS digitally controlled oscillator for clock recovery and frequency synthesis PLLs

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