Low-voltage Low-power CMOS IF Programmable Gain Amplifier

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Zhang

et al. 2011

A 0.13um CMOS 1.5-to-2.15GHz low power transmitter front-end with direct quadrature voltage modulation for SDR applications is presented. The SDR transmitter front-end consists of PGA, passive RC filter, direct quadrature voltage modulator, 25%-duty-cycle LO generator and programmable PA-Driver with reconfigurable operation frequency bands. An on-chip transformer with switchedcapacitor array provides the wide-band reconfigurable frequency band covering and differential-to-single-ended conversion. The passive voltage mixer with 25%-duty-cycle LO implements the frequency up-conversion with low noise and low conversion loss. The SDR transmitter front-end has been implemented in 0.13um CMOS, the measured results show that this front-end could provide 22dB gain with a step of 2dB and output higher than 0dBm power across 1.5-to-2.15GHz frequency range with a maximum power consumption of 42mW. The die area is 1.6mm*1.2mm.

Section: A Low Power Pgamentioning

confidence: 99%

A 0.13µm CMOS 1.5-to-2.15GHz low power transmitter front-end for SDR applications

Sun

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Zhang

et al. 2011

“…4 shows the schematic of the two-stage PGA. The single-stage PGA is based on a simple differential gain amplifier with a negative feedback Gmboosted source-degeneration differential pair [6]. The negative feedback Gm-boosting input stage can reduce the equivalent source resistance of M1 and improve the linearity of the input stage; thus, it is very attractive for high-frequency and lowpower operation.…”

Section: A Pga Blockmentioning

confidence: 99%

A Low-Power High-Data-Rate ASK IF Receiver With a Digital-Control AGC Loop

IEEE Trans. Circuits Syst. II

Wang

2010

A low-power high-data-rate ASK IF receiver is proposed. It consists of one digital-control automatic-gain-control (AGC) loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of the programmable-gain amplifier (PGA) in the AGC loop is discretely adjusted by a gain-control block to eliminate the multidigit analog-to-digital converter. Due to the high sensitivity of the ASK detector, a large controllable input range can be obtained in the AGC loop. The ASK IF receiver has been implemented in 0.18-μm CMOS, and the overall current consumption is 1.21 mA with a supply voltage of 1.8 V. The ASK receiver achieves a 2-Mb/s data rate with an IF carrier frequency of 10 MHz, and an input signal amplitude ranges from 180 μV to 900 mV.Index Terms-Amplitude-shift keying (ASK) detector, automatic gain control (AGC), CMOS, low power, receiver.

“…4 shows the schematic of the two-stage PGA. The single stage PGA is based on a simple differential gain block with source degeneration [4], which can be used to control the gain by changing the degeneration resistor. Yin+ and Yin-are the input IF signals, while Yfb+ and Vfb-are the feedback signals from the Gm-C low-pass filter.…”

Section: B Ask Detectormentioning

confidence: 99%

A low power high date rate ASK IF receiver

2009 IEEE 8th International Conference on ASIC

Wang

2009

verify the feasibility of the proposed idea. Abstract -A low power high data rate ASK IF receiver is proposed. It consists of one digital-control AGC loop and an ASK detector. By utilizing the scrambler concept in the digital communication systems, the gain of PGA in the AGC loop is adjusted discretely by a gain control block to eliminate the multi-digit AID converter. The ASK IF receiver has been implemented in O.18/1m CMOS and the overall power consumption is 2.175mW with a supply voltage of 1.8V. The operating frequency is 10M, and the data rate is 2Mbps. The amplitude of detectable input signal can range from 5/1 V to 900mV 1 .