Low-voltage ZnO double-gate thin film transistor circuits

Abstract

We report here double-gate ZnO thin film transistor (TFT) circuits with operation at low voltage. TFTs with low voltage operation have been reported previously, but often use very thin (few nm thick) gate dielectric which may limit manufacturability [1]. Oxide semiconductor-based TFTs have been extensively studied as competitive candidates for next-generation display technology and other large-area electronics. For many applications, operation at voltages compatible with low-voltage CMOS is important. Doublegate TFTs are of interest because they allow threshold voltage tuning, improved device performance, and circuit applications like mixers. [2,3] We have previously reported bottom-gate ZnO TFTs and circuits fabricated on glass and flexible polymeric substrates using plasma enhanced atomic layer deposition (PEALD) [4,5]. Here we report double-gate ZnO TFTs and circuits fabricated on glass substrates using PEALD with a maximum process temperature of 200 ˚C. Compared to bottom-gate ZnO TFTs, doublegate ZnO TFTs have higher mobility, and reduced substhreshold slope. In these devices, the top gate can be used to vary the bottom-gate threshold voltage by more than 4 V. This allows the logic transition point for circuits to be adjusted as desired and allows logic operation at low voltage. 15 stage double-gate ZnO TFT ring oscillators operate well with V DD = 1.2 V, I D = 32 µA, and propagation delay of 2.1 µs/stage. Figure 1 shows a schematic cross-section of a double-gate ZnO TFT. To fabricate the devices, a 100 nm Cr layer was deposited on borosilicate glass by sputtering and patterned by wet etching to form the bottom gates. Next, 32 nm thick Al 2 O 3 and 10 nm thick ZnO layers were deposited by PEALD and patterned by wet etching. Next, Ti source and drain contacts were deposited by sputtering and patterned by lift-off. An O 2 plasma step was used prior to Ti deposition to reduce contact resistance. Al 2 O 3 (32 nm thick) deposited by ALD at 200 °C was used for the top-gate dielectric and patterned by wet etching. 100 nm thick Cr was deposited by sputtering and patterned by wet etching to form the top gates. Linear region I D versus V GS and I D versus V DS characteristics are shown in figure 1 for a TFT with L = 20 µm, W = 200 µm, t oxbottom = t oxtop = 32 nm. Both bottom-gate with V topgate = 0 and top and bottom gates connected together device characteristics are shown in the figure. Bottom-gate operated TFTs have linear region mobility of 27 cm 2 /V⋅s; with top and bottom gates connected together the linear region mobility increases to 33 cm 2 /V⋅s. Figure 2 shows threshold voltage tuning of more than 4 V for bottom-gate TFT characteristics by varying the top-gate voltage from -3 V to 3V.The schematic diagram and micrograph of a double-gate TFT inverter with L drive = 5 µm, W drive = 50 µm, L load = 5 µm, W load = 10 µm (β ratio = 5) is shown in Figure 3. Top and bottom gates are connected together and to the source for the load TFT. The top gate of the drive TFT is varied to tune the bottom-gate TFT threshold ...

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