Low -Warpage Encapsulants for Wafer Level Packaging

Chao, Jay; Zhang, Rong; Grimes, David A.; Shim, Kail; Do, Tu; Ma, Yijia; Trichur, Ramachandran

doi:10.23919/iwlpc52010.2020.9375882

Cited by 1 publication

(1 citation statement)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fully protected CSP was first implemented with processes such as M-series utilizing FO. 1,2 These processes require costly and complex die reconstitution, expensive tapes, molding, and other operations that can be avoided for non-fan-out devices to provide the cost-effective high reliability 6S format needed for high-performance higher pin count and/or thin silicon chips. 3 American Semiconductor's Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected CSP, fan-in (FI), and chiplets.…”

Section: Introductionmentioning

confidence: 99%

WLCSP Fully Protected Fan-In Reliability

Hackler,

Prack

2024

IMAPSource Proceedings

View full text Add to dashboard Cite

A strong supply chain requires higher performance and lower cost processes. DCA conventionally referred to as WLCSP has been used for low density devices, however for higher density devices reliability concerns have emerged. Six-side protected, aka “6S or fully protected”, CSP is a rapidly growing market. Fully protected CSP was first implemented with processes such as M-series utilizing FO. These processes require costly and complex die reconstitution, expensive tapes, molding, and other operations. These steps can be eliminated in a P-WLCSP process to provide the cost-effective high reliability 6S format needed for high-performance higher pin count and/or thin silicon chips. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected CSP, fan-in, and chiplets. Protected FI process innovations can improve performance in power devices, RF switches, photonic IC (PIC), die stacking and thin board applications. The P-WLCSP process incorporates the best of DCA (simplicity) and FO (protection) while incorporating advanced manufacturing processes to lower cost and improve performance. This paper builds on the SoP-TM process release announced at the 2023 Device Packaging Conference earlier this year with the addition of reliability characterization beyond first silicon data for electrical test chips. Reliability data such as accelerated stress tests, die strength, operating lifetime and thermal testing are key areas of investigation for the new P-WLCSP technology that will be presented. The presentation will also include and update for ultra-thin device reliability test methods under consideration for new NIST standards.

show abstract

Section: Introductionmentioning

confidence: 99%