Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477)
DOI: 10.1109/lpe.1999.799425
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Lower and upper bounds an the switching activity in scheduled data flow graphs

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Cited by 6 publications
(3 citation statements)
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“…In [6], the authors present an optimal algorithm for assigning operations to existing resources in the case of data flow graphs (DFGs) without loops. More recently, [14] shows that the case of DFGs with loops is NP-complete, and proposes an approximate algorithm. A key difference with our case is that in high-level synthesis, the assignment is done at synthesis time, so data values of operands are not available, but profile-data may be.…”
Section: Related Workmentioning
confidence: 99%
“…In [6], the authors present an optimal algorithm for assigning operations to existing resources in the case of data flow graphs (DFGs) without loops. More recently, [14] shows that the case of DFGs with loops is NP-complete, and proposes an approximate algorithm. A key difference with our case is that in high-level synthesis, the assignment is done at synthesis time, so data values of operands are not available, but profile-data may be.…”
Section: Related Workmentioning
confidence: 99%
“…In [6], the authors present an optimal algorithm for assigning operations to existing resources in the case of data flow graphs (DFGs) without loops. More recently, [11] shows that the case of DFGs with loops is NP-complete, and proposes an approximate algorithm. The case of a modern superscalar processor employing out-of-order execution and speculation is much more complicated, however.…”
Section: Related Workmentioning
confidence: 99%
“…In [6], the authors present an optimal algorithm for assigning operations to existing resources in the case of data flow graphs (DFGs) without loops. More recently, [14] shows that the case of DFGs with loops is NP-complete, and proposes an approximate algorithm. A key difference with our case is that in high-level synthesis, the assignment is done at synthesis time, so A runtime scheme for reducing power consumption in custom logic has been proposed [8] that reduces power in the case that operand bit-widths are often less that the maximum data width.…”
Section: Energy Modeling In Functional Unitsmentioning
confidence: 99%