&lt;italic&gt;PhLock:&lt;/italic&gt; A Cache Energy Saving Technique Using Phase-Based Cache Locking

Adegbija, Tosiron; Gordon‐Ross, Ann

doi:10.1109/tvlsi.2017.2757477

Cited by 6 publications

(2 citation statements)

References 27 publications

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“…This small increase in power dissipation can be managed through power-saving techniques, such as those found in refs. [17,18,[23][24][25], thus not prohibiting the adoption of DPCAM in multi-core systems.…”

Section: Authormentioning

confidence: 99%

New Content Addressable Memory Architecture for Multi-Core Applications

Abumwais,

Obaid

2024

Computer Memory and Data Storage

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The future of massively parallel computation appears promising due to the emergence of multi- and many-core computers. However, major progress is still needed in terms of the shared memory multi- and many-core systems, specifically in the shared cache memory architecture and interconnection network. When multiple cores try to access the same shared module in the shared cache memory, issues arise. Cache replacement methods and developments in cache architecture have been explored as solutions to this. This chapter introduces the Near-Far Access Replacement Algorithm (NFRA), a new hardware-based replacement technique, as well as a novel dedicated pipeline cache memory design for multi-core processors, known as dual-port content addressable memory (DPCAM). The experiments show that the access latency for write/read operations of a DPCAM is lower than that of a set-associative (SA) cache memory, with the latency of a write operation staying the same regardless of the size of the DPCAM. It is estimated that the power usage will be 7% greater than a SA cache memory of the same size.

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Section: Authormentioning

confidence: 99%

New Content Addressable Memory Architecture for Multi-Core Applications

Abumwais,

Obaid

2024

Computer Memory and Data Storage

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“…They show that their technique leads to significant reduction in miss rate and energy saving. They extended their work in [12] and proposed a new cache locking method to achieve energy saving with minimal performance loss. The method can be used for both instruction and data cache.…”

Section: A Static Cache Lockingmentioning

confidence: 99%

A Dynamic Instruction Cache Locking Approach for Minimizing Worst Case Execution Time of a Single Task

et al. 2020

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In real time embedded system, the embedded software often consists of a set of concurrent tasks, and such tasks are generally subject to timing constraints. In order to satisfy all the timing constraints, precisely predicting the WCET of a task is essential for the task scheduler to construct a feasible schedule for a task set. Caches have been widely used to bridge the gap between high speed processors and relatively slower off-chip memory. However, caches make it extremely harder to predict precise WCET (Worst Case Execution Time ) of a task for the simple reason that it is difficult to predict if each cache access is a cache hit or miss. Cache locking is a mechanism which disables the replacement policy of caches and locks some contents (instruction or data) in the caches, such that the accesses to those contents become fully predictable and the WCET of a task is easier to predict. Furthermore, cache locking is also an effective technique to reduce the WCET of a task by locking appropriate contents in the caches. In this paper, we investigate the WCET-aware I-cache (Instruction cache) locking problem and propose an ILP-based (Integer Linear Programming) dynamic I-cache locking approach for reducing the WCET of a task. Our approach not only select locking contents which have largest benefit for reducing WCET of a task, but also finds a good locking point for each locked instruction such that extra execution time spend on locking instructions is also minimized. We have implemented this approach and compared it with two state-of-theart I-cache locking approaches, the longest path based dynamic cache locking approach proposed in and the min-cut based dynamic locking approach proposed in by using MRTC benchmark suite. The experimental results show that our approach performs better for each benchmark. Compared to the longest path based dynamic approach, our approach achieves the average improvements of 5.8%, 13.8%, 16.1% and 12.6% for the 256B, 512B, 1KB and 2KB caches, respectively. Compared to the min-cut based dynamic approach, our approach achieves the average improvements of 2.2%, 7.6%, 8.2% and 6.4% for the 256B, 512B, 1KB and 2KB caches, respectively.INDEX TERMS Cache locking, real-time systems, worst-case-executing-time.

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