<p>Implementation of PPI with Nano Amorphous Oxide Semiconductor Devices for Medical Applications</p>

Abstract

Background: Electronic devices which mimic the functionality of biological synapses are a large step to replicate the human brain for neuromorphic computing and for numerous medical research investigations. One of the representative synaptic behaviors is paired-pulse facilitation (PPF). It has been widely investigated because it is regarded to be related to biological memory. However, plasticity behavior is only part of the human brain memory behavior.Methods: Here, we present a phenomenon which is opposite to PPF, i.e., paired-pulse inhibition (PPI), in nano oxide devices for the first time. The research here suggests that rather than being enhanced, the phenomena of memory loss would also be possessed by such electronic devices. The device physics mechanism behind memory loss behavior was investigated. This mechanism is sustained by historical memory and degradation manufactured by device trauma to regulate characteristically stimulated origins of artificial transmission behaviors.Results: Under the trauma of a memory device, both the signal amplitude and signal time stimulated by a pulse are lower than the first signal stimulated by a previous pulse in the PPF, representing a new scenario in the struggle for memory. In this way, more typical human brain behaviors could be simulated, including the effect of age on latency and error generation, cerebellar infarct, trauma and memory loss pharmacological actions (such as those caused by hyoscines and nitrazepam). Conclusion: Thus, this study developed a new approach for implementing the manner in which the brain works in semiconductor devices for improving medical research.

Artificial Synapse Based on Oxygen Vacancy Migration in Ferroelectric‐Like C‐Axis‐Aligned Crystalline InGaSnO Semiconductor Thin‐Film Transistors for Highly Integrated Neuromorphic Electronics

“…This is the mechanism mimicking the electrical properties of biological synapse such as IPSC, PPD, and LTP at V DS = 0.1 V. The advantage of this device is that it is possible to use a conventional gate insulator such as SiO 2 . Compared to previous works, [ 17,28–34 ] this work can get rid of the inevitable use of a functional gate insulator to implement synaptic characteristics. Accordingly, large scale integration of the synaptic devices can be possible.…”

“…[22][23][24] Note that short-channel transistors can be available with oxide TFTs. [25,26] Table 1 shows the summary of the synaptic transistors based on MO semiconductors such as IGZO, [27][28][29][30] ITO, [31] IZO, [32] ZnO [33] and In 2 O 3 . [34] They use electrolytes or ferroelectric materials such as chitosan, [32] Ta 2 O 3 , [33] nanoparticles SiO 2 , [27] Gd 2 O 3 , [34] Al 2 O 3 [28] and HfZrO x [29] as gate insulator (GI) to…”