&lt;title&gt;20-GFLOPS QR processor on a Xilinx Virtex-E FPGA&lt;/title&gt;

Walke, R.; Smith, R. Scott; Lightbody, Gaye

doi:10.1117/12.406508

Cited by 13 publications

(7 citation statements)

References 10 publications

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“…The applications are: QR which is a matrix decomposition algorithm [19], Stereo vision which is a 1-D motion estimation algorithm [10], and Optical Flow which is a generic image restoration algorithm [11]. For each application, we give for a particular node in the network the size of the ROM Looking at Table 1, we conclude that for large domains, the ROM approach is non practical.…”

Section: The Rom Controllermentioning

confidence: 99%

Deriving efficient control in Process Networks with Compaan/Laura

Derrien¹,

Turjan²,

Zissulescu³

et al. 2008

IJES

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Abstract:At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map rapidly and efficiently signal processing applications written in Matlab onto reconfigurable platforms. In this chain, first the Matlab code is converted automatically to an executable Kahn Process Network (KPN) specification [6], then a tool called Laura transforms the PN specification into a design implementation described as synthesizable VHDL.The applications targeted by Compaan are usually data-flow intensive, requiring large computational power. Therefore, an important issue in Laura is the derivation of efficient and scalable hardware control structures. This control is based on an abstract representation given as parametrized polytopes. Although this representation can be directly translated into nested guarded for-loops (very suitable for software implementation) its mapping to hardware is much more difficult. In this paper we investigate the opportunities of deriving different hardware realizations for this control, and explore the trade off between speed and resource usage.

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Section: The Rom Controllermentioning

confidence: 99%

Deriving efficient control in Process Networks with Compaan/Laura

Derrien¹,

Turjan²,

Zissulescu³

et al. 2008

IJES

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show abstract

“…To explain the hints the profiler implemented in Laura presented and how that effects design decisions, we now consider the QR case, which is widely used in signal processing applications [10]. The Matlab code for the QR algorithm that can be processed by Compaan is presented in Figure 4.…”

Section: Qr: a Case Studymentioning

confidence: 99%

Increasing Pipelined IP Core Utilization in Process Networks Using Exploration

Zissulescu

Kienhuis

Deprettere

2004

Field Programmable Logic and Application

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Abstract. At Leiden Embedded Research Center, we are building a tool chain called Compaan/Laura that allows us to do fast mapping of applications written in Matlab onto reconfigurable platforms, such as FPGAs, using IP cores to implement the data-path of the applications. A particular characteristic of the derived networks is the existence of selfloops. These selfloops have a large impact on the utilization of IP cores in the final hardware implementation of a PN, especially if the IP cores are deeply pipelined. In this paper, we present an exploration methodology that uses feedback provided by the Laura tool to increase the utilization of IP cores embedded in our PN network. Using this exploration, we go from 60MFlops to 1,7GFlops for the QR algorithm using the same number of resources except for memory.

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“…Substantial savings in operator size are obtained by reducing the wordlength of the mantissa and exponent of our floating-point numbers to that which is just sufficient to meet the accuracy requirements of our systems. The level of optimization possibly depends on the application, but it has been found that relatively low wordlengths are possible, and using 14-bit mantissa we obtain in excess of 20 GigaFLOPS of computation on a single FPGA (Walke et al, 1999).…”

Section: Floating-point Qr Decomposition Implementationmentioning

confidence: 99%

Compilation from Matlab to process networks realised in FPGA

Harriss

Walke

Kienhuis

et al. 2001

Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256)

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Abstract.Compaan is a software tool that is capable of automatically translating nested loop programs, written in Matlab, into parallel process network descriptions suitable for implementation in hardware. In this article, we show a methodology and tool to convert these process networks into FPGA implementations. We will show that we can in principle obtain high performing realizations in a fraction of the design time currently employed to realize a parameterized implementation. This allows us to rapidly explore a range of transformations, such as loop unrolling and skewing, to generate a circuit that meets the requirements of a particular application. The QR decomposition algorithm is used to demonstrate the capability of the tool. We present results showing how the number of clock cycles and calculations-persecond vary with these transformations using a simple implementation of the function units. We also provide an indication of what we expect to achieve in the near future once the tools are completed and applied the transformations to parallel, highly pipelined implementations of the function units.

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<title>20-GFLOPS QR processor on a Xilinx Virtex-E FPGA</title>

Cited by 13 publications

References 10 publications

Deriving efficient control in Process Networks with Compaan/Laura

Deriving efficient control in Process Networks with Compaan/Laura

Increasing Pipelined IP Core Utilization in Process Networks Using Exploration

Compilation from Matlab to process networks realised in FPGA

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