&lt;title&gt;Advanced process control for poly-Si gate etching using integrated CD metrology&lt;/title&gt;

Kota, Gowri P.; Luque, Jorge; Vahedi, Vahid; Khathuria, Ashok; Dziura, T. G.; Levy, Ady

doi:10.1117/12.487635

Cited by 10 publications

(5 citation statements)

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“…Figure 7(c) shows the Áb variations for the CD-SEM and the OCD tool just after the experiments using only the CD-SEM; the difference between the Áb variations for the CD-SEM and OCD tool was found to be very small. Taking into account the fact that the instability of the pre etch CD measurement by OCD measurement tool is almost negligible 3) and that the instability of the post etch CD measurement can be ignored because of the periodic qualification, the Áb variations comprise mainly the process drift of the RIE.…”

Section: Resultsmentioning

confidence: 99%

“…1) Lot-to-lot and wafer-to-wafer gate linewidth variations can be reduced using model-based advanced process control (APC) techniques in the gate plasma etching process. [2][3][4] One of the reasons for gate linewidth variations is variations in thephoto resist pattern widths prior to gate etching. Using feedforward control of the resist pattern profile information obtained by critical dimension (CD) measurement tools such as the critical-dimension measurement scanning electron microscope (CD-SEM) and optical critical dimension (OCD) scatterometry measurement tool, variations in resist pattern widths can be compensated for at the plasma trimming step.…”

Section: Introductionmentioning

confidence: 99%

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Evaluation of Errors in Feedback Control Based on Persistence Prediction in Model-Based Process Controller System for Deep Sub-100 nm Gate Fabrication

Goto

Makabe

2006

Jpn. J. Appl. Phys.

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Using model-based advanced process control (APC) in the gate etching process, gate linewidth variations that are caused by variations in the photo resist linewidth are reduced by feedforward control of the photo resist linewidth that is obtained by a critical dimension (CD) measurement tool. Both long-term process drift in the etching process and long-term instability of the CD measurement tool lead to variations in the process model for APC. These process model variations result in gate linewidth variations and are attenuated by feedback control using the etch CD bias from the previously processed lot. We used a lot-to-lot model-based APC system and a critical dimension scanning electron microscope (CD-SEM) in a deep sub-100 nm gate fabrication line to investigate long-term variations in the process model over a period of six months, and to study how much the variations are reduced by feedback control based on persistence prediction methods using the etch CD bias for the pilot wafer from the currently processed lot. The process model uses the linear relationship between the etch CD bias and the gas mixture ratio at the gate linewidth plasma trimming step, and the gradient is almost constant over the term. The spread in the long-term variation in the process model was 8.12 nm. The variation mainly included process drift in the plasma etcher, and the persistence of the etch CD bias in the lot after processing was significantly lost beyond approximately one week. When using feedback control based on the persistence prediction method using the etch CD bias for the pilot wafer from the currently processed lot, the standard deviation of the feedback error was 0.50 nm of 1σ. On the other hand, when calculating feedback control with the lot-mean etch CD bias from the lot processed immediately before the currently processed lot, the standard deviation of the feedback error was estimated to be 0.82 nm of 1σ. When performing feedback with the etching shift value of the pilot wafers, the percentage of lots whose post etch CD value fell within the range of ±1 nm from the target value was higher by 20% than the simulated value of the percentage of lots in which feedback was calculated with the etch CD bias of the previously processed lots.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Evaluation of Errors in Feedback Control Based on Persistence Prediction in Model-Based Process Controller System for Deep Sub-100 nm Gate Fabrication

Goto

Makabe

2006

Jpn. J. Appl. Phys.

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“…A linear optimizer was implemented in Matlab and used to find the optimal zone controller offsets change which minimizes (6).…”

Section: A DI Cdu Control Methodology With Cd-to-offset Modelmentioning

confidence: 99%

Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment

Zhang

Poolla

Spanos

2007

IEEE Trans. Semicond. Manufact.

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Across-wafer gate critical dimension (CD) uniformity impacts chip-to-chip performance variation vis-à-vis speed and power. Performance specification for across-wafer CD uniformity has become increasingly stringent as linewidth decreases to 90 nm and below. This paper presents a novel approach to improve across-wafer gate CD uniformity through the lithography and etch process sequence. The proposed approach is to compensate for upstream and downstream systematic CD variation components in the litho-etch process sequence by optimizing across-wafer post exposure bake (PEB) temperature profiles. More precisely, we first construct a temperature-to-offset model that relates the PEB temperature profiles to the setpoint offsets of multi-zone PEB plates. A second model relating across-wafer CD to setpoint offsets of PEB plates is then identified from CD scanning electron microscope measurements. Post-develop and post-etch CD uniformity enhancement methodologies are then proposed based on the CD-to-offset model and temperature-to-offset models. The temperature-to-offset model is determined to be more appropriate for use in CD uniformity control due to its superior fidelity and portability as compared with the CD-to-offset model. We demonstrate that about 1-nm reduction in standard deviation of post-etch CD variation was achieved in the verification experiment, which validated the efficacy of proposed CD uniformity control approach.Index Terms-Constrained quadratic programming, critical dimension (CD), critical dimension uniformity (CDU), multiobjective optimization, multizone PEB bake plate, plasma etch bias signature, postexposure bake (PEB), process control, process modeling.

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“…Many papers have discussed the application of scatterometry to chip manufacturing lines. [1][2][3] The higher throughput and the ability to obtain information on pattern profile as well as CD are attractive for CD control. However, although optical scatterometry has several advantages compared with conventional SEM metrology, it also has inherent disadvantages.…”

Section: Introductionmentioning

confidence: 99%

In-line CD metrology with combined use of scatterometry and CD-SEM

et al. 2006

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Measurement characteristics in scatterometry and CD-SEM for lot acceptance sampling of inline critical dimension (CD) metrology were investigated by using a statistical approach with Monte Carlo simulation. By operation characteristics curve analysis, producer's risk and consumer's risk arising from sampling were clarified. Single use of scatterometry involves a higher risk, such risk being particularly acute in the case of large intra-chip CD variation because it is unable to sufficiently monitor intra-chip CD variation including local CD error. Substituting scatterometry for conventional SEM metrology is accompanied with risks, resulting in the increase of unnecessary cost. The combined use of scatterometry and SEM metrology in which the sampling plan for SEM is controlled by scatterometry is a promising metrology from the viewpoint of the suppression of risks and cost. This is due to the effect that CD errors existing in the distribution tails are efficiently caught.

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<title>Advanced process control for poly-Si gate etching using integrated CD metrology</title>

Cited by 10 publications

References 0 publications

Evaluation of Errors in Feedback Control Based on Persistence Prediction in Model-Based Process Controller System for Deep Sub-100 nm Gate Fabrication

Evaluation of Errors in Feedback Control Based on Persistence Prediction in Model-Based Process Controller System for Deep Sub-100 nm Gate Fabrication

Across Wafer Critical Dimension Uniformity Enhancement Through Lithography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment

In-line CD metrology with combined use of scatterometry and CD-SEM

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