<title>Decomposition of 2D shuffle multistage interconnection networks</title>

<title>Self-routing in &gt;2D shuffle networks by d-tuples</title>

“…In the following we start to compare dimension-independent and dimension-dependent switches by means of the small examples devoted to the interconnection of 8x8-arrays (Table 3). However, the solution with dimension-dependent 8x8-switches additionally requires a costly interconnection scheme [3] and is thus appropriate 1ff the switching/processing nodes are separated Fig. From Table 3 we may conclude that the 4x4-switches (1st column) are best from the point of view of a minimum complexity of RTs followed by dimension-independent 8x8-switches.…”

“…An interesting feature of 2-D MINs with dimension-dependent switches and interconnections is the decomposition without loss offunctionality [2,3,4]. Dependent on the particular application and available technology 2-D MINs with dimension-independent switches or dimension-dependent switches and interstage interconnections may be applied (Remark 4).…”

“…Table 9. .j-5632x0, 512x(±1), (±2), (±3) (±4)(±5) (±6) II 2816x0,256x(±1,2,-3,-5), 768x(-2) C 5632x0, 512x(±2), (±3), (±4) (5,7,-6) I 2816x0,256x(1,±3,-4,6), 768x(-2) D 4608 xO, 512x(1,7,-4), 1024x (±3,5), 1536x(-6) J 2560x0,512 x(2,-3,4), 1024x (3,6), 512x(-8,9,-E 5120x0, 512x (2,4,-3,-5,-6,-8), 1024x (-1), 1536x(-6) K 2816x0, 256x (1,4,7), 512x(2,3), 768x(-8) F 5120x0, 512x(3,-1,-4,-8), 1024x(4,-6), 1536x5 L 512x(1,±2,4,5,'7,-8) G 5120x0, 512x(2, -5,-6,-7,-8), 3072x4 M 512x(2,6), 256x (3), 768x(4), 1024x (-8) .j-5632x0, 512x(±1), (±2), (±3) (±4)(±5) (±6) II 2816x0,256x(±1,2,-3,-5), 768x(-2) C 5632x0, 512x(±2), (±3), (±4) (5,7,-6) I 2816x0,256x(1,±3,-4,6), 768x(-2) D 4608 xO, 512x(1,7,-4), 1024x (±3,5), 1536x(-6) J 2560x0,512 x(2,-3,4), 1024x (3,6), 512x(-8,9,-E 5120x0, 512x (2,4,-3,-5,-6,-8), 1024x (-1), 1536x(-6) K 2816x0, 256x (1,4,7), 512x(2,3), 768x(-8) F 5120x0, 512x(3,-1,-4,-8), 1024x(4,-6), 1536x5 L 512x(1,±2,4,5,'7,-8) G 5120x0, 512x(2, -5,-6,-7,-8), 3072x4 M 512x(2,6), 256x (3), 768x(4), 1024x (-8) …”

“…The common strategy in MINs, applied to decrease the number of stages (NS), is to increase the size of the switches. In this way, we are able to board and local/wide area network level [3]. Throughout the ongoing work, these switches are indicated as dimension-independent according to (i) the increase of the size of the switches and (ii) constant 2-D interstage interconnections [1].…”

“…However, the advantage of setting up arbitrary large systems by means of many small systems might not balance the drawbacks which are (i) a costly interconnection scheme for the switches and (ii) the composition of the RT by a d-tuple DAD introduced by the RTC. However, deflection angles and interconnection schemes for dimension-dependent switches [2][3][4] will not be discussed throughout the paper. However, in the case of distributed 2-D switching/processing systems, where the processing units are separated geographicaily or if only small wafers are available, there is no alternative and thus the analysis of these combinatorial effects is reasonable.…”