<title>High-speed Viterbi decoding design for wireless LAN systems</title>

Abstract

This paper describes the hardware design of a high speed Viterbi decoder for the IEEE 802.11a Wireless Local Area Networks (WLAN) application. A fully parallel Add-Compare-Select (ACS) and trace-back architecture is presented to achieve the decoding rate up to 54Mbps. Modulation scheme and coding rate dependent quntaization accuracy for soft decision Viterbi decoding is explored and a hardware implementation scheme with run-time configurable bit-length for soft decision is then proposed to reduce the system power consumption.