&lt;title&gt;Matrix Triangularization By Systolic Arrays&lt;/title&gt;

Gentleman, W. Morven; Kung, H. T.

doi:10.1117/12.932507

Cited by 356 publications

(105 citation statements)

References 5 publications

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“…An alternative is to use a parallel version of Givens method. There are many papers on this subject especially within the study of systolic arrays of processors [13,14,28]. Here we present a variant of these techniques that is suitable for parallel processors with far more computing power in a single processor than considered in the systolic array case.…”

Section: Qr Factorization Of a Sparse Matrixmentioning

confidence: 99%

Linear algebra on high performance computers

Dongarra

Sorensen

1986

Applied Mathematics and Computation

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Section: Qr Factorization Of a Sparse Matrixmentioning

confidence: 99%

Linear algebra on high performance computers

Dongarra

Sorensen

1986

Applied Mathematics and Computation

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“…The ensuing linear detection or SIC on systolic array will be discussed in Section V. In the following discussion, we assume that the channel matrix has been QR decomposed. It is known that QRD can be implemented in systolic array based on a series of Givens rotations, since Given rotations can be executed in a parallel manner [20]- [22]. Since the conventional systolic array for QRD usually contains square root operations, which are computationally intensive in hardware implementation, a square-root-free systolic QRD based on Squared Givens rotations (SGR) can be used (the interested readers can refer to [29], [35]).…”

Section: Systolic Array For Two Lattice-reduction Algorithmsmentioning

confidence: 99%

“…Since all PEs can work simultaneously, the latency is shorter than with a single processor system, and the results of D are outputted in parallel. Systolic algorithms and the corre-sponding systolic arrays have been designed for a number of linear algebra algorithms, such as matrix triangularization [20], matrix inversion [21] , adaptive nulling [22], recursive leastsquare [23], [24], etc. An overview of systolic designs for several computationally demanding linear algebra algorithms for signal processing and communications applications was recently published in [25].…”

Section: Introductionmentioning

confidence: 99%

Systolic arrays for lattice-reduction-aided mimo detection

2011

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Abstract-Multiple-input, multiple-output (MIMO) technology provides high data rate and enhanced QoS for wireless communications. Since the benefits from MIMO result in a heavy computational load in detectors, the design of low-complexity sub-optimum receivers is currently an active area of research. Lattice-reduction-aided detection (LRAD) has been shown to be an effective low-complexity method with near-ML performance. In this paper we advocate the use of systolic array architectures for MIMO receivers, and in particular we exhibit one of them based on LRAD. The "LLL lattice reduction algorithm" and the ensuing linear detections or successive spatial-interference cancellations can be located in the same array, which is considerably hardware-efficient. Since the conventional form of the LLL algorithm is not immediately suitable for parallel processing, two modified LLL algorithms are considered here for the systolic array. LLL algorithm with full-size reduction (FSR-LLL) is one of the versions more suitable for parallel processing. Another variant is the all-swap lattice-reduction (ASLR) algorithm for complex-valued lattices, which processes all lattice basis vectors simultaneously within one iteration. Our novel systolic array can operate both algorithms with different external logic controls. In order to simplify the systolic array design, we replace the Lovász condition in the definition of LLL-reduced lattice with the looser Siegel condition. Simulation results show that for LRaided linear detections, the bit-error-rate performance is still maintained with this relaxation. Comparisons between the two algorithms in terms of bit-error-rate performance, and average FPGA processing time in the systolic array are made, which shows that ASLR is a better choice for a systolic architecture, especially for systems with a large number of antennas.

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“…The ORD algorithm of Luk 2 , 3 is similar to that of Gentlemen and Kung 6 in that it is based on a triangular array of.*processors. However, it is organized to permit a smoother data flow when used for both a ORD and SVD or GSVD.…”

Section: Algorithmsmentioning

confidence: 99%

Architecture of the Systolic Linear Algebra Parallel Processor (SLAPP)

Symanski¹

1986

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<title>Matrix Triangularization By Systolic Arrays</title>

Cited by 356 publications

References 5 publications

Linear algebra on high performance computers

Linear algebra on high performance computers

Systolic arrays for lattice-reduction-aided mimo detection

Architecture of the Systolic Linear Algebra Parallel Processor (SLAPP)

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