&lt;title&gt;Modelling and synthesis of automata in HDLs&lt;/title&gt;

Chmielewski, S.; Węgrzyn, Marek

doi:10.1117/12.714537

Cited by 3 publications

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“…However, in the presented method synchronization of the concurrent processes is realized by the additional signals as transition conditions. Implementation of decomposed Petri nets onto set of SM-components can be carried out in different methods [6]. In the presented paper a modeling of automata in Verilog is focused.…”

Section: Verilog Modeling and Synthesismentioning

confidence: 99%

9 PeNLogic – System for Concurrent Logic Controllers Design

Węgrzyn

2011

Design of Digital Systems and Devices

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Abstract. In the paper the CAD system dedicated for modeling, verification, and synthesis of concurrent controllers modeled by interpreted Petri net is presented. Petri net model can be prepared as graph or as textual form. Controllers specified by Petri nets can be analyzed and implemented using method suitable for such model. For verification of Petri net another part of system is used. Moreover, the results of verification are decomposition of net into several communicating state machines (as finite state machines, FSMs). After verification it is possible to transform Petri net model into HDLs model (VHDL and Verilog) and alternatively into EDIF or XNF netlist format. Such prepared models are also simulated and synthesized using other academic or commercial CAD systems. The system has been developing at University of Zielona Góra. Development of new methods of modeling, verification and synthesis has been contributed to make an attempt the new integrated version of the system. In addition, using of Java environment gives opportunity to work out the system that is platform independent. IntroductionThe specific application often dictates the system design requirements, such as modularity and flexibility. In general, the design procedure involves the integration of analytical and graphical descriptions. Graphical descriptions, such as control-interpreted Petri nets [11], SFC (Sequential Function Chart) [8] and Grafcet [7], provide established techniques for proper system designs. They have helped industrial engineers to understand the system behavior and performance over many years.A behavioral representation describes the system's functionality independently of its implementation. It treats a system as a black box, and defines how the black box responds to any combination of input values. The process of designing a system proceeds from a behavioral specification (SFC diagram or Petri net) to a programmable logic implementation (FPGA, Field Programmable Gate Array). A design in purely behavioral form, like a Petri net, is converted into an intermediate rule-based description, void of any technology-specific implementation details. The final FPGA implementation is generated by automatic synthesis using CAD

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Section: Verilog Modeling and Synthesismentioning

confidence: 99%

9 PeNLogic – System for Concurrent Logic Controllers Design

Węgrzyn

2011

Design of Digital Systems and Devices

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“…Elements of the mentioned models are shown in Fig. 1; for the details see [9], [12], [13]. In our experiments we have used the Mealy state machines, which are (in a sense) more general than the Moore automata.…”

Section: Finite State Machinesmentioning

confidence: 99%

“…8. Such structure requires less logical blocks (note that it is true only for Mealy FSMs) [13], [14]. Common minimization of two systems of Boolean functions requires (according to the interpretation by Altera Quartus) description of all of them in the same process.…”

Section: Y_assignmentmentioning

confidence: 99%

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Experimental Comparison of Synthesis Tools Altera Quartus II and Synthagate

Węgrzyn¹,

Karatkevich²

2013

International Journal of Electronics and Telecommunications

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Abstract-The paper presents comparison between efficiency of an industrial FPGA design software tool Altera Quartus II and similar design software tool Synthagate by Syntezza company of an academic origin. The experiments were performed using a series of examples describing the Mealy finite state machines; onehot state encoding was used in all cases. Area (number of used logical blocks) was the main parameter used for the comparison. Influence of the way of FSM description (in VHDL language) on the quality of synthesis was studied. The obtained results show that Synthagate in almost all cases performs synthesis more efficiently and essentially quicker than Altera Quartus. Section I presents motivation of the research. Section II reminds the notion of FSM. Section III describes problems which had to be solved to provide correctness of experimental comparison. Section IV presents some details about state encoding way used in the experiments. In Section V, the experimental results are presented. Section VI describes the problems related to the comparison which still have to be solved. Section VII presents the conclusions from the experiments. Section VIII suggests possible reasons of the detected situation.

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Petri Net Decomposition Approach for Partial Reconfiguration of Logic Controllers

Węgrzyn

2006

IFAC Proceedings Volumes

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<title>Modelling and synthesis of automata in HDLs</title>

Cited by 3 publications

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9 PeNLogic – System for Concurrent Logic Controllers Design

9 PeNLogic – System for Concurrent Logic Controllers Design

Experimental Comparison of Synthesis Tools Altera Quartus II and Synthagate

Petri Net Decomposition Approach for Partial Reconfiguration of Logic Controllers

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