&lt;title&gt;Monolithic 2.5-Gb/s clock and data recovery circuit based on silicon bipolar technology&lt;/title&gt;

Pallotta, Andrea; Centurelli, Francesco; Loriga, Francesco; Trifiletti, Alessandro

doi:10.1117/12.321886

Cited by 3 publications

(3 citation statements)

References 5 publications

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“…In a first version of the CDR IC [9], the linear section of the limiting amplifier on the data input side of the chip is comprised of two differential stages, exploiting the topology presented in [13] to enhance the bandwidth, for an overall 40 dB gain with a bandwidth in excess of 2 GHz. We used the passive input-matching and offset-cancelling topology in Fig.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…Higher gain can be obtained at the expense of input matching, with the topology in [9], that requires larger external capacitors and is found to be more sensitive to the effect of the bond wires used to connect them.…”

Section: Parameter Valuementioning

confidence: 96%

“…An alternative way to achieve input matching with better offset suppression when using the offsetcancelling network shown in Fig. 1 can also be devised [9]. This technique does not require the additional resistors inside the dashed box and input matching is obtained by placing 50 resistors on the input side of the feedback loop (R 1 = 50 = R S ), so that the dc gain of the feedback network is now:…”

Section: Analysis Of Passive Offset-cancelling Networkmentioning

confidence: 99%

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Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

Centurelli¹,

Pallotta

Tommasino

et al. 2006

Analog Integr Circ Sig Process

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The diffusion of optical communication systems in the access network and for short-haul datacom applications requires the use of low-cost plastic packages: the functional block most affected is the limiting amplifier, that is often the first stage of the Clock and Data Recovery (CDR) IC.In this paper we illustrate the design issues of the input-matching and offset-cancelling network for a differential limiting amplifier for optical communication systems, with particular emphasis on the effect of bond wires. We discuss the limitations of passive feedback networks when used both for offset suppression and for input matching, and propose a topology that overcomes such limitations by using an active feedback loop. A 50 -loaded differential pair is used to achieve input matching and high offset suppression, and its buffering action desensitizes the input matching from the effect of the bond wires connecting off-chip filtering capacitors. Very good performance even with low cost plastic packages can be achieved by solving the trade-off between power consumption, offset suppression and the value of the low-pass filtering capacitors.Design examples of CDR IC's for 2.5 Gb/s optical systems are presented to compare the proposed topology with solutions based on passive feedback networks.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: Parameter Valuementioning

confidence: 96%

Section: Analysis Of Passive Offset-cancelling Networkmentioning

confidence: 99%

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Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

Centurelli¹,

Pallotta

Tommasino

et al. 2006

Analog Integr Circ Sig Process

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A compact 3R-receiver module for short-haul SDH STM-16 systems

Centurelli

Magliocco

Pallotta³

et al. 2001

J. Lightwave Technol.

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This paper describes a complete 3R optical receiver module for synchronous digital hierarchy (SDH) STM-16 short-haul systems, housed in a 20-pin dual-in-line (DIL) ceramic package. The module includes an InGaAs p-i-n photodiode, a commercial GaAs transimpedance amplifier, and a custom-made silicon bipolar frequency- and phase-locked loop (FPLL)-based clock and data recovery (CDR) circuit. The fiber pigtail is actively aligned to the photodiode by using a proprietary technology that uses a silicon-based optical submount assembly (OSA). The use of a clock recovery circuit based on an FPLL allows avoiding an external low-frequency reference clock and achieving a root-mean square (rms) jitter of 0.075 UI. The module requires two supply voltages of 5 V and 4.5 V, for a total power dissipation of 930 mW, and has a total volume below 0.75 cm3 (24.7x9.9x3 mm3). Measurements have shown full compatibility with SDH standards

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Input-matching and offset-compensation network for limiting amplifiers in optical communication systems

Centurelli¹,

Pallotta²,

Tommasino³

et al.

1999 Southwest Symposium on Mixed-Signal Design (Cat. No.99EX286)

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A novel topology for the offset-compensation and input-matching network of high gain differential amplifiers, tolerant with respect to parasitic effects of bonding wires, is presented. An IC for an optical receiver featuring this network has been designed, and simulations and measurements show high offset suppression (20 dB) and good input matching (Gamma in < -10 dB) over a wide bandwidth (100 kHz - 3 GHz) when considering bonding wires some millimeters long

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<title>Monolithic 2.5-Gb/s clock and data recovery circuit based on silicon bipolar technology</title>

Cited by 3 publications

References 5 publications

Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

A compact 3R-receiver module for short-haul SDH STM-16 systems

Input-matching and offset-compensation network for limiting amplifiers in optical communication systems

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