&lt;title&gt;Optimal detector&lt;/title&gt;

Field Programmable Logic and Application

2004

Abstract. Hybrid reconfigurable systems integrate DSPs and general purpose processors with an FPGA fabric. These systems may support features such as efficient start-up and shut-down, dynamic voltage scaling, and reconfiguration, that are exploited for energy-efficient application design. Duty cycle is the proportion of time during which a system is operated. Multi-rate applications consist of tasks that execute at different rates. Designing an energy-efficient hybrid reconfigurable system with duty cycle specification that implements a multi-rate application using devices with multiple operating states presents several challenges such as modeling, rapid performance estimation, and efficient design space exploration. We present a design framework that addresses these challenges. Using our framework, we illustrate the design of two energy efficient systems: automated target detection and adaptive beamforming.

Section: Illustrative Examplesmentioning

confidence: 99%

Section: Illustrative Examplesmentioning

confidence: 99%

See 1 more Smart Citation

A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems

Field Programmable Logic and Application

2004

“…We consider a personnel detection (video surveillance) application for our third example [Singer 2002]. The personnel detection algorithm is required to process input in real time and hence there is a hard latency requirement.…”

Section: Energy-efficient Architecture Selection For a Personnel Detementioning

confidence: 99%

A model-based extensible framework for efficient application design using FPGA

ACM Trans. Des. Autom. Electron. Syst.

2007

For an FPGA designer, several choices are available in terms of target FPGA devices, IP-cores, algorithms, synthesis options, runtime reconfiguration, degrees of parallelism, among others, while implementing a design. Evaluation of design alternatives in the early stages of the design cycle is important because the choices made can have a critical impact on the performance of the final design. However, a large number of alternatives not only results in a large number of designs, but also makes it a hard problem to efficiently manage, simulate, and evaluate them. In this article, we present a framework for FPGA-based application design that addresses the aforementioned issues. This framework supports a hierarchical modeling approach that integrates application and device modeling techniques and allows development of a library of models for design reuse. The framework integrates a high-level performance estimator for rapid estimation of the latency, area, and energy of the designs. In addition, a design space exploration tool allows efficient evaluation of candidate designs against the given performance requirements. The framework also supports extension through integration of widely used tools for FPGA-based design while presenting a unified environment for different target FPGAs. We demonstrate our framework through the modeling and performance estimation of a signal processing kernel and the design of end-to-end applications.

“…We consider a target detection application [7] to illustrate HiPerE. The application design problem is to select the most energy-efficient FPGA between Xilinx Virtex-II and Actel ProASIC P LUS [1,8].…”

Section: Illustrative Examplementioning

confidence: 99%

Duty Cycle Aware Application Design using FPGAs

12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

Duty cycle is the proportion of time a device is active. Therefore, based on the duty cycle specification, application (implemented using the device) execution can be modeled as alternate active and inactive phases. For FPGAs, during inactive phases, energy is dissipated due to leakage current and clock signal distribution. If the duration of the inactive phases is significantly larger than that of the active phases, optimizing energy dissipation during inactive phases contributes significantly towards the overall energy efficiency. We present a design tool for the evaluation of various optimization techniques such as shutting down FPGAs, transitioning to a low power state, or leaving as it is to minimize overall energy dissipation. We illustrate the tool through energy efficient design of a target tracking application using FPGAs. MotivationMobile devices operate in energy constrainedenvironments. Therefore, energy efficient application design using FPGAs is an emerging area of research [3,4]. Duty cycle specification allows modeling of a period of execution as alternate active and inactive phases. Low duty cycle refers to a period of execution when the duration of the inactive phases is significantly larger than that of the active phases. Mobile phones and systems implementing automatic target recognition and tracking are often associated with low duty cycles [2]. Energy dissipation (e.g. due to leakage current), for systems with low duty cycle, during inactive phases can contribute significantly towards the overall energy dissipation. Therefore, the tradeoff between energy dissipation due to shutting down (and starting up) and idling needs to be evaluated [3].There are several tools and techniques for application design using FPGAs. Xilinx System Generator for Simulink provides a high-level interface for application design using pre-compiled libraries of signal processing kernels [8].[5] presents a compiler, PACT HDL, which given a high-level algorithm in C, generates power and performance optimized design for FPGAs. However, these tools do not focus on the behavior of the target FPGA based on duty cycle specification. To the best of our knowledge, there are no tools available that takes into consideration duty cycle specifications during application design. In this paper, we discuss Highlevel Performance Estimator (HiPerE) that allows application designs based on duty cycle specification. Duty Cycle Aware Application DesignWe assume that application input consists of several frames where processing of one frame corresponds to one active phase. Input rate is the rate (in Hz) at which the frames are provided as input. Input rate and the latency required to process a single frame specify duty cycle. Input rate can vary. We assume that a set of target FPGAs, an application modeled as a data flow graph, a set of designs of the application on the target FPGAs, and a duty cycle specification are provided as input. Given an application that consists of a set of tasks, a design specifies the implementation and the tar...