Each of the 12 MCA boards is a stand-alone, self-gated. pulse-height-analysis circuit that consists of the follo_ing: We describe a 12-channel VMEbus-based pulse-height • a programmable gain amplifier (PGA); analysis board that was designed for use in a high-rate, • a low-level discriminator ILLD); multidetector, gamma-ray imaging system. This module was • a charge integrator; designed to minimize dead-time losses and to allow all key • an ADC: and parameters to be software controlled. Gamma-ray detectors are • a first-in-first-out (FIFO) memory. connected directly to this module, eliminating the need for The MZ8135 CPU board (a commercial. 3U-sized, 68030 additional electronics. CPU running at 40 MHz with 1 megabyte of dual-ported memory) reads data from and controls the 12 MCA boards. |. [NTRODUCTION Programs are down loaded into the CPU's memory, which reads and processes the data, making it available to processors The need to instrument an array of 64 BGO detectors and on the VMEbus via its dual-ported memory. provide very low dead-time and fast-processing capabilities led The following relates briefly one channel's operation: to the design of a VMEbus-based pulse-height analysis board, (1) When an input pulse from the detector goes over the LLD the VMEMCA. Several of these boards are used in the data threshold, the charge integrator begins to integrate a acquisition system [1] developed for the nuclear resonance delayed version of that pulse• (The integration time is absorption project [2]. High single-channel instantaneous software programmable from 100 ns to 3 Its.) rates, up to 125-kHz, and low signal-to-noise ratios prompted (2) Once the integration time has been completed, the 8-bit us to design a module that could quickly process each over-flash ADC digitizes the output level of the charge threshold detector pulse. The charge-integration technique integrator and stores the data in the FIFO memory. The allows straightforward processing of each detector pulse dead-time contribution, not including integration time, of without the need for charge preamps and shaping amplifiers, the circuit is <100 ns, which is the sum of lhe This technique also reduces the signal-processing time to the digitization time and the integrator's reset time. time it takes to integrate the charge from the photomultiplier (3) Concurrent with step 2, the CPU section reads each tube (PMT). Another feature of the module is the dc-coupled channel's FIFO sequentially and processes data into analog signal path, which minimizes base-line shift, histograms and regions of interest (ROls). To _.:eepup Our BGO detectors, with an energy resolution of-15% for with the average input rate, the CPU must be _ble to 137Cs ' enabled us to use 8-bit flash analog-to-digital process events at a rate of 300 kHz. converters (ADCs). This resulted in adequate en "rgy resolution The parameters of the VMEMCA board can be changed with fast processing times, under software control; they are the L.LD set9oint, the gain, the integration time, and the low-and hig...