&lt;title&gt;Spatiotemporal partitioning of computational structures onto configurable computing machines&lt;/title&gt;

Chau

ACM Trans. Reconfigurable Technol. Syst.

et al. 2015

A design approach is proposed to automatically identify and exploit runtime reconfiguration opportunities with optimised resource utilisation by eliminating idle functions. We introduce Reconfiguration Data Flow Graph, a hierarchical graph structure enabling reconfigurable designs to be synthesised in three steps: function analysis, configuration organisation, and runtime solution generation. The synthesised reconfigurable designs are dynamically evaluated and selected under various runtime conditions. Three applicationsbarrier option pricing, particle filter, and reverse time migration-are used in evaluating the proposed approach. The runtime solutions approximate their theoretical performance by eliminating idle functions and are 1.31 to 2.19 times faster than optimised static designs. FPGA designs developed with the proposed approach are up to 43.8 times faster than optimised CPU reference designs and 1.55 times faster than optimised GPU designs.

Section: Related Workmentioning

confidence: 99%

Automating Elimination of Idle Functions by Runtime Reconfiguration

Chau

ACM Trans. Reconfigurable Technol. Syst.

et al. 2015

“…A configuration containing all application functions is referred to as the static design. With Virtex-6 FPGAs, if previous partitioning algorithms [7,8,9] are applied, the static design would be the final configuration, as it achieves maximum task-level parallelism and minimises the communication overhead. As listed in Table 2, the optimal partition is up to 1.45 times faster, and 1.42 times more energy efficient, than the static designs.…”

Section: Optimal Reconfiguration Solutionmentioning

confidence: 99%

“…The problem is formulated as a Integer Nonlinear Programming (INLP) model [8] to minimise the communication efforts between partitioned segments. Spatial partitioning is covered in [9] to support multiple devices. The motivation for these partitioning algorithms is that there are not enough resources to accommodate the targeted applications.…”

Section: Run-time Reconfigurationmentioning

confidence: 99%

Exploiting run-time reconfiguration in stencil computation

22nd International Conference on Field Programmable Logic and Applications (FPL)

Luk

et al. 2012

Stencil computation is computationally intensive and required by many applications. This paper proposes an approach to exploit run-time reconfigurability of field-programmable accelerators for stencil computation. System throughput is optimized by partitioning, analysing and scheduling tasks in applications to remove idle functions. To evaluate the proposed approach, Reverse Time Migration (RTM), a high performance application, is developed. Our optimized runtime reconfigurable solution, which targets a Virtex-6 FPGA in a Maxeler MAX3424A system, can achieves an improved throughput of 102.8 GFlop/s, up to two orders of magnitude faster than the CPU reference designs, 1.59 times faster than the best published GPU and FPGA results, and 1.45 times faster than an optimized static implementation.

“…The problem is formulated as an Integer Non-linear Programming (INLP) model [7] to minimise communication between partitioned segments. Spatial partitioning is covered in [8] to support multiple devices. The motivation for these partitioning algorithms is to fit large applications into small FPGAs, while our work focus on how to identify and eliminate inefficient functions, using run-time reconfiguration.…”

Section: Related Workmentioning

confidence: 99%

“…Various scheduling algorithms have been proposed to ensure correct execution of nodes in a graph [6], [8]. The ALAP level [9] G i .alap is assigned to simplify communication between different configurations.…”

Section: A Function Property Extractionmentioning

confidence: 99%

Automating Elimination of Idle Functions by Run-Time Reconfiguration

Chau

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

et al. 2013

A design approach is proposed to automatically identify and exploit run-time reconfiguration opportunities while optimising resource utilisation. We introduce Reconfiguration Data Flow Graph, a hierarchical graph structure enabling reconfigurable designs to be synthesised in three steps: function analysis, configuration organisation, and run-time solution generation. Three applications, based on barrier option pricing, particle filter, and reverse time migration are used in evaluating the proposed approach. The run-time solutions approximate the theoretical performance by eliminating idle functions, and are 1.31 to 2.19 times faster than optimised static designs. FPGA designs developed with the proposed approach are up to 28.8 times faster than optimised CPU reference designs and 1.55 times faster than optimised GPU designs.