<title>Technological limitations in submicron on-chip interconnect</title>

Abstract

The trend of the performance degradafions, noise and reliability issues and their potential solutions are analyzed for the submicron ULSI interconnect lines. To analyze these submicron interconnect lines, a new paradigm(HIVE) for fast and accurate 2-D and 3-D interconnect capacitances and resistances calculation is developed. The analysis, using these interconnect parameters from HIVE, shows that a copper(Cu) line will improve the elewomigrations, but not the interconnect delay and cross-talk noise significantly. The low temperature operation improve the interconnect delay and electromigralion, but it increases the cost of system packaging. The optimum approach will be the combination of additional layers of non-scaled metal lines in a higher level, low permittivity interlevel dielectri; and the use of repeaters to maximize the performance, noise and reliability and to minimize the risk and cost.