LUT Input Reordering to Reduce Aging Impact on FPGA LUTs

Ebrahimi, Mohammad; Sadeghi, Rezgar; Navabi, Zainalabedin

doi:10.1109/tc.2020.2974955

Cited by 6 publications

(2 citation statements)

References 15 publications

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“…The LUT node is a SRAM memory for storing a description of a function, which is written into this memory in the form of program code during the programming of the FPGA component. In the widespread case of decomposition of computations into functions for no more than four arguments, the LUT node has 16 bits of memory, addressed by the dcba2 code, which is fed to 4 inputs D, C, B, A [16].…”

Section: Background For Fpga Development In Critical Applicationsmentioning

confidence: 99%

Improving Fpga Components of Critical Systemsbased on Natural Version Redundancy

Drozd¹,

Ruciński²,

Zashcholkin³

et al. 2021

AAIT

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The article is devoted to the problem of improving FPGA (Field Programmable Gate Array) components developed for safety related systems. FPGA components are improved in the checkability of their circuits and the trustworthiness of the results calculated on them to support fault-tolerant solutions, which are basic in ensuring the functional safety of critical systems. Fault-tolerant solu tions need protection from sources of multiple failures, which include hidden faults. They can be accumulated in significant quanti ties during a long normal operation and disrupt the functionality of fault-tolerant circuits with the onset of the most responsible emer gency mode. Protection against hidden faults is ensured by the checkability of the circuits, which is aimed at the manifestation of faults and therefore must be supported in conjunction with the trustworthiness of the results, taking into account the decrease in trustworthiness in the event of the manifestation of faults. The problem of increasing the checkability of the FPGA component in normal operation and the trustworthiness of the results calculated in the emergency mode is solved by using the natural version re dundancy inherent in the LUT-oriented architecture (Look-Up Table). This redundancy is manifested in the existence of many ver sions of the program code that preserve the functionality of the FPGA component with the same hardware implementation. The checkability of the FPGA component and the trustworthiness of the calculated results are considered taking into account the typical failures of the LUT-oriented architecture. These malfunctions are investigated from the standpoint of the consistency of their mani festation and masking, respectively, in normal and emergency modes on versions of the program code. Malfunctions are identified with bit distortion in the memory of the LUT units. Bits that are only observed in emergency mode are potentially dangerous because they can hide faults in normal mode. Moving potentially dangerous bits to checkable positions, observed in normal mode, is per formed by choosing the appropriate versions of the program code and organizing the operation of the FPGA component on several versions. Experiments carried out with the FPGA component using the example of an iterative array multiplier of binary codes have shown the effectiveness of using the natural version redundancy of the LUT-oriented architecture to solve the problem of hidden faults.

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Section: Background For Fpga Development In Critical Applicationsmentioning

confidence: 99%

Improving Fpga Components of Critical Systemsbased on Natural Version Redundancy

Drozd¹,

Ruciński²,

Zashcholkin³

et al. 2021

AAIT

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show abstract

“…Hence, it is essential to understand the main aging mechanisms of FPGAs [4][5][6]. Meanwhile, estimating the aging trends of age-related faults before they occur is crucial for developing aging prevention/mitigation actions to avoid circuit failures [7,8].…”

Section: Introductionmentioning

confidence: 99%

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

Huang

Wang

et al. 2022

Sensors

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Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the phenomenon of circuit aging has become more significant with the sharp reduction in the process size of FPGAs. Aging results in FPGA performance degradation over time and, ultimately, hard faults. However, few studies have focused on understanding aging mechanisms or estimating the aging trend of 28-nm FPGAs. For this, we used a ring oscillator (RO)-based test structure to extract data and build a dataset that could be used to predict aging trends and determine the primary aging mechanisms of 28-nm FPGAs. Moreover, we proposed a correction method to correct temperature-induced measurement errors in accelerated tests. Furthermore, we employed four machine learning (ML) technologies that were based on accurate measurement datasets to predict FPGA aging trends. In the experiment, 24 XILINX 7-series FPGAs (28 nm) were evaluated for 10+ years of circuit operation using accelerated tests. The results showed that the aging effects of negative-bias temperature instability (NBTI) was the primary aging mechanism. The correction method proposed in this paper could effectively eliminate measurement errors. In addition, the minimum prediction error rate of the ML model was only 0.292%.

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BAS: A BTI-based aging aware synthesis in FPGAs

Abednazari

Beitollahi

2022

Microelectronics Reliability

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LUT Input Reordering to Reduce Aging Impact on FPGA LUTs

Cited by 6 publications

References 15 publications

Improving Fpga Components of Critical Systemsbased on Natural Version Redundancy

Improving Fpga Components of Critical Systemsbased on Natural Version Redundancy

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

BAS: A BTI-based aging aware synthesis in FPGAs

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