2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS) 2016
DOI: 10.1109/dtis.2016.7483881
|View full text |Cite
|
Sign up to set email alerts
|

MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding

Abstract: In this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are designed. In the first design, a regular redundant carry-save MAC unit is designed using well known carry-save techniques. In the second design, a hybrid design is proposed to exploit fast carry chains of the FPGA together with double carry-save output encoding. The proposed scheme exploits fast-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks to increase the performance. T… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2

Citation Types

0
2
0

Year Published

2017
2017
2024
2024

Publication Types

Select...
2
1
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(2 citation statements)
references
References 9 publications
0
2
0
Order By: Relevance
“…al. [10] efficiently implemented compressor trees [11] on FPGA, which is more efficient in terms of area and speed, and is made possible by using the specialized carry chains of linear array compressor tree. Linear array compressor trees lead to marked improvements in speed compared to carry propagate adder (CPA) approaches and, in general, with no additional hardware cost.…”
Section: Introductionmentioning
confidence: 99%
See 1 more Smart Citation
“…al. [10] efficiently implemented compressor trees [11] on FPGA, which is more efficient in terms of area and speed, and is made possible by using the specialized carry chains of linear array compressor tree. Linear array compressor trees lead to marked improvements in speed compared to carry propagate adder (CPA) approaches and, in general, with no additional hardware cost.…”
Section: Introductionmentioning
confidence: 99%
“…This 1-bit full adder can be used to add multiple operands by using multiple numbers of full adders [8]. Addition of more than two numbers of operands calls for a multi-operand adder [10,11]. In 2005, R. D Kenney and M. J Schulte [1] introduces and analyzes three techniques for performing fast operands addition.…”
Section: Introductionmentioning
confidence: 99%