Abstract:The
lack of physical information at the early gate-level Netlist
makes timing accuracy a significant challenge. Advancing in the physical
design flow reduces the timing inaccuracy gap in the cell’s
delay estimation, where the physical layout information is no longer
estimated. This paper aims to improve the cell delay accuracy of Oasys-RTL Synthesis by predicting the cell’s output
capacitance using Machine Learning algorithms. We trained and tested
various ML Regression algorithms to predict the Oasys-RTL cell… Show more
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