Machine-Learning Based Congestion Estimation for Modern FPGAs

Maarouf, Dani; Al-Hyari, Abeer; Abuowaimer, Ziad; Martin, Timothy J.; Gunter, Andrew; Gréwal, Gary; Areibi, Shawki; Vannelli, A.

doi:10.1109/fpl.2018.00079

Cited by 33 publications

(25 citation statements)

References 11 publications

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“…Routing estimation has also been studied extensively in [13] where a heuristicbased method predicts routing demand that various nets in a design exert on routing resources of an FPGA. Two very recent works propose congestion estimation on FPGA designs [14,15]. In [15], the authors made prediction based on three (feature) parameters.…”

Section: Related Literaturementioning

confidence: 99%

Congestion Prediction in FPGA Using Regression Based Learning Methods

Goswami

Bhatia

2021

Electronics

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Design closure in general VLSI physical design flows and FPGA physical design flows is an important and time-consuming problem. Routing itself can consume as much as 70% of the total design time. Accurate congestion estimation during the early stages of the design flow can help alleviate last-minute routing-related surprises. This paper has described a methodology for a post-placement, machine learning-based routing congestion prediction model for FPGAs. Routing congestion is modeled as a regression problem. We have described the methods for generating training data, feature extractions, training, regression models, validation, and deployment approaches. We have tested our prediction model by using ISPD 2016 FPGA benchmarks. Our prediction method reports a very accurate localized congestion value in each channel around a configurable logic block (CLB). The localized congestion is predicted in both vertical and horizontal directions. We demonstrate the effectiveness of our model on completely unseen designs that are not initially part of the training data set. The generated results show significant improvement in terms of accuracy measured as mean absolute error and prediction time when compared against the latest state-of-the-art works.

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Section: Related Literaturementioning

confidence: 99%

Congestion Prediction in FPGA Using Regression Based Learning Methods

Goswami

Bhatia

2021

Electronics

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“…Recently, the use of machine learning methods has gained popularity also in this domain [22]- [28]. Maarouf et al [23] used tens of millions of routed grid cells from large FPGAs for training and testing. They used features such as wirelength per area as well as pin count and cut nets per region, and applied various machine learning algorithms to estimate the actual congestion in each grid cell after placement, without the need to route the chip.…”

Section: Related Workmentioning

confidence: 99%

“…Alhyari et al [24] trained and evaluated a convolutional neural network model on tens of thousands of images based on several hundred benchmarks from Xilinx to predict the routability of the designs based on the congestion heatmap during placement. In the same team, Szentimrey et al [27] combined a deep learning-based congestion management model with the congestion estimation approach proposed in [23] and the routability prediction algorithm from [24] and used them in the GPlace3.0 framework [29] to achieve better runtime and quality of results. Pui et al [26] also used machine-learning-based models to estimate the routing congestion for a given circuit placement on an FPGA along with detailed placement techniques (two-step clock legalization and chain move) to better optimize wirelength and meet emerging clocking architectural constraints of modern FPGAs, like Xilinx UltraScale.…”

Section: Related Workmentioning

confidence: 99%

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

et al. 2021

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Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While software developers can use high-level synthesis (HLS) to speed up registertransfer level (RTL) code generation from C++ or OpenCL source code, placement and routing issues, such as congestion, can still prevent achieving an FPGA programming bitstream or dramatically reduce the FPGA implementation performance. Congestion reports from physical design tools refer to thousands of RTL signal names instead of developer-accessible identifiers and statements, considerably complicating the developer understanding and resolution of the issues at the source level. We propose a high-level back-annotation flow that summarizes the routing congestion issues at the source level by analyzing the reports from the FPGA physical design tools and the internal debugging files of the HLS tools. Our flow describes congestion using comments back-annotated on the source code and identifies if the congestion causes are the on-chip memories or the DSP units (multipliers/adders), which are the shared resources very often associated with routing problems on FPGAs. We demonstrate on realistic large designs how the information provided by our flow helps to quickly spot congestion causes at the source level and to solve them using appropriate HLS directives.

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“…The results demonstrate that the accuracy of this model in predicting congestion is less than actual by 70%. The approach presented by Maarouf et al increases the estimation accuracy through utilizing three new congestion related features with shorter runtime [35]. To estimate the routing congestion in high level synthesis, Zhao et al propose a ML model to resolve congestion in source code through utilizing informative physical features [26].…”

Section: B Utilizing ML Approaches To Increase the Efficiency Of Fpga Designsmentioning

confidence: 99%

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

2021

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Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the FPGAs with power-gating ability is a promising way to effectively address the power-consumption obstacle. However, the main challenge when implementing power gating is in choosing the clusters of resources in a way that would allow the most power-saving opportunities. In this paper, we take advantage of machine learning approaches, such as K-means clustering, to propose efficient algorithms for creating power-gating clusters of FPGA routing resources. In the first group of proposed algorithms, we employ K-means clustering and exploit the utilization pattern of routing resources. In the second group of algorithms, we enhance the power-gating efficiency by minimizing the power overhead introduced by power-gating logic and by taking into account the size of routing multiplexers, which influences the power-gating efficiency. Finally, we enhance and further develop the baseline FPGA routing algorithm to be aware and take advantage of power gating opportunities. The experimental results on Titan benchmark suite and the latest Intel Stratix-IV FPGA architecture in VTR 8.0 show that our approaches achieve an improvement of about 70%, on average, in reducing the FPGA static power consumption over the best power-gating approaches proposed in the previous studies.INDEX TERMS Field-programmable gate arrays, static power consumption, power gating, routing algorithm, machine learning

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Machine-Learning Based Congestion Estimation for Modern FPGAs

Cited by 33 publications

References 11 publications

Congestion Prediction in FPGA Using Regression Based Learning Methods

Congestion Prediction in FPGA Using Regression Based Learning Methods

High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

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